ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediate 

These instructions used an 'r' in their bit list, but a 'd' in the operands.
This commit is contained in:
Pokechu22 2022-05-22 17:15:49 -07:00
parent b349254ff4
commit 4dc7208195
3 changed files with 31 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Source/Core/Core/DSP/Interpreter/DSPIntArithmetic.cpp
View File

@ -45,7 +45,7 @@ void Interpreter::clrl(const UDSPInstruction opc)
//----
// ANDCF $acD.m, #I
// 0000 001r 1100 0000
// 0000 001d 1100 0000
// iiii iiii iiii iiii
// Set logic zero (LZ) flag in status register $sr if result of logic AND of
// accumulator mid part $acD.m with immediate value I is equal to I.
@ -61,7 +61,7 @@ void Interpreter::andcf(const UDSPInstruction opc)
}
// ANDF $acD.m, #I
// 0000 001r 1010 0000
// 0000 001d 1010 0000
// iiii iiii iiii iiii
// Set logic zero (LZ) flag in status register $sr if result of logical AND
// operation of accumulator mid part $acD.m with immediate value I is equal
@ -144,7 +144,7 @@ void Interpreter::cmpaxh(const UDSPInstruction opc)
}
// CMPI $amD, #I
// 0000 001r 1000 0000
// 0000 001d 1000 0000
// iiii iiii iiii iiii
// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
// Although flags are being set regarding whole accumulator register.
@ -320,7 +320,7 @@ void Interpreter::notc(const UDSPInstruction opc)
}
// XORI $acD.m, #I
// 0000 001r 0010 0000
// 0000 001d 0010 0000
// iiii iiii iiii iiii
// Logic exclusive or (XOR) of accumulator mid part $acD.m with
// immediate value I.
@ -337,7 +337,7 @@ void Interpreter::xori(const UDSPInstruction opc)
}
// ANDI $acD.m, #I
// 0000 001r 0100 0000
// 0000 001d 0100 0000
// iiii iiii iiii iiii
// Logic AND of accumulator mid part $acD.m with immediate value I.
//
@ -354,7 +354,7 @@ void Interpreter::andi(const UDSPInstruction opc)
}
// ORI $acD.m, #I
// 0000 001r 0110 0000
// 0000 001d 0110 0000
// iiii iiii iiii iiii
// Logic OR of accumulator mid part $acD.m with immediate value I.
//
@ -489,8 +489,8 @@ void Interpreter::addaxl(const UDSPInstruction opc)
UpdateSR64Add(acc, acx, GetLongAcc(dreg));
}
// ADDI $amR, #I
// 0000 001r 0000 0000
// ADDI $amD, #I
// 0000 001d 0000 0000
// iiii iiii iiii iiii
// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
//

16
Source/Core/Core/DSP/Jit/x64/DSPJitArithmetic.cpp
View File

@ -53,7 +53,7 @@ void DSPEmitter::clrl(const UDSPInstruction opc)
//----
// ANDCF $acD.m, #I
// 0000 001r 1100 0000
// 0000 001d 1100 0000
// iiii iiii iiii iiii
// Set logic zero (LZ) flag in status register $sr if result of logic AND of
// accumulator mid part $acD.m with immediate value I is equal to I.
@ -88,7 +88,7 @@ void DSPEmitter::andcf(const UDSPInstruction opc)
}
// ANDF $acD.m, #I
// 0000 001r 1010 0000
// 0000 001d 1010 0000
// iiii iiii iiii iiii
// Set logic zero (LZ) flag in status register $sr if result of logical AND
// operation of accumulator mid part $acD.m with immediate value I is equal
@ -221,7 +221,7 @@ void DSPEmitter::cmpaxh(const UDSPInstruction opc)
}
// CMPI $amD, #I
// 0000 001r 1000 0000
// 0000 001d 1000 0000
// iiii iiii iiii iiii
// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
// Although flags are being set regarding whole accumulator register.
@ -458,7 +458,7 @@ void DSPEmitter::notc(const UDSPInstruction opc)
}
// XORI $acD.m, #I
// 0000 001r 0010 0000
// 0000 001d 0010 0000
// iiii iiii iiii iiii
// Logic exclusive or (XOR) of accumulator mid part $acD.m with
// immediate value I.
@ -482,7 +482,7 @@ void DSPEmitter::xori(const UDSPInstruction opc)
}
// ANDI $acD.m, #I
// 0000 001r 0100 0000
// 0000 001d 0100 0000
// iiii iiii iiii iiii
// Logic AND of accumulator mid part $acD.m with immediate value I.
//
@ -505,7 +505,7 @@ void DSPEmitter::andi(const UDSPInstruction opc)
}
// ORI $acD.m, #I
// 0000 001r 0110 0000
// 0000 001d 0110 0000
// iiii iiii iiii iiii
// Logic OR of accumulator mid part $acD.m with immediate value I.
//
@ -686,8 +686,8 @@ void DSPEmitter::addaxl(const UDSPInstruction opc)
}
}
// ADDI $amR, #I
// 0000 001r 0000 0000
// ADDI $amD, #I
// 0000 001d 0000 0000
// iiii iiii iiii iiii
// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
//

30
docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
View File

@ -1217,12 +1217,12 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{ADDI}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{0000} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{0000} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
\begin{DSPOpcodeFormat}
ADDI $amR, #I
ADDI $amD, #I
\end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription}
@ -1356,7 +1356,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{ANDCF}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{1100} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{1100} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -1384,7 +1384,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{ANDF}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{1010} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{1010} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -1412,7 +1412,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{ANDI}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{0100} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{0100} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -1953,7 +1953,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{CMPI}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{1000} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{1000} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -3629,7 +3629,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{ORI}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{0110} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{0110} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -4286,7 +4286,7 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\begin{DSPOpcode}{XORI}
\begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{0000} & \monobitbox{4}{001r} & \monobitbox{4}{0010} & \monobitbox{4}{0000} \\
\monobitbox{4}{0000} & \monobitbox{4}{001d} & \monobitbox{4}{0010} & \monobitbox{4}{0000} \\
\monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii} & \monobitbox{4}{iiii}
\end{DSPOpcodeBytefield}
@ -4960,13 +4960,13 @@ Instruction & Opcode & Page \\ \hline
\OpcodeRow{0000 0010 1101 cccc}{RETcc}
\OpcodeRow{0000 0010 1111 cccc}{RTIcc}
\OpcodeRowSkip
\OpcodeRow{0000 001r 0000 0000 iiii iiii iiii iiii}{ADDI}
\OpcodeRow{0000 001r 0010 0000 iiii iiii iiii iiii}{XORI}
\OpcodeRow{0000 001r 0100 0000 iiii iiii iiii iiii}{ANDI}
\OpcodeRow{0000 001r 0110 0000 iiii iiii iiii iiii}{ORI}
\OpcodeRow{0000 001r 1000 0000 iiii iiii iiii iiii}{CMPI}
\OpcodeRow{0000 001r 1010 0000 iiii iiii iiii iiii}{ANDF}
\OpcodeRow{0000 001r 1100 0000 iiii iiii iiii iiii}{ANDCF}
\OpcodeRow{0000 001d 0000 0000 iiii iiii iiii iiii}{ADDI}
\OpcodeRow{0000 001d 0010 0000 iiii iiii iiii iiii}{XORI}
\OpcodeRow{0000 001d 0100 0000 iiii iiii iiii iiii}{ANDI}
\OpcodeRow{0000 001d 0110 0000 iiii iiii iiii iiii}{ORI}
\OpcodeRow{0000 001d 1000 0000 iiii iiii iiii iiii}{CMPI}
\OpcodeRow{0000 001d 1010 0000 iiii iiii iiii iiii}{ANDF}
\OpcodeRow{0000 001d 1100 0000 iiii iiii iiii iiii}{ANDCF}
\OpcodeRowSkip
\OpcodeRow{0000 0010 1100 1010}{LSRN}
\OpcodeRow{0000 0010 1100 1011}{ASRN}