Remove accessType from BackPatch's signature in favor of getting it from DisassembleMov.
It isn't easily accessible with sigaction or Mach exceptions (well, requires an additional system call in the latter), and isn't necessary. (and get rid of the enum, because it's only used once, and the comments are more expressive than enum names)
This commit is contained in:
parent
e198e201e4
commit
4c3230bcde
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@ -4,7 +4,7 @@
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#include "x64Analyzer.h"
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#include "x64Analyzer.h"
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bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int accessType)
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bool DisassembleMov(const unsigned char *codePtr, InstructionInfo *info)
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{
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{
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unsigned const char *startCodePtr = codePtr;
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unsigned const char *startCodePtr = codePtr;
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u8 rex = 0;
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u8 rex = 0;
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@ -12,11 +12,11 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int acc
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u8 codeByte2 = 0;
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u8 codeByte2 = 0;
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//Check for regular prefix
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//Check for regular prefix
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info.operandSize = 4;
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info->operandSize = 4;
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info.zeroExtend = false;
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info->zeroExtend = false;
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info.signExtend = false;
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info->signExtend = false;
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info.hasImmediate = false;
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info->hasImmediate = false;
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info.isMemoryWrite = false;
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info->isMemoryWrite = false;
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u8 modRMbyte = 0;
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u8 modRMbyte = 0;
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u8 sibByte = 0;
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u8 sibByte = 0;
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@ -26,7 +26,7 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int acc
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if (*codePtr == 0x66)
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if (*codePtr == 0x66)
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{
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{
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info.operandSize = 2;
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info->operandSize = 2;
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codePtr++;
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codePtr++;
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}
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}
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else if (*codePtr == 0x67)
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else if (*codePtr == 0x67)
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@ -40,7 +40,7 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int acc
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rex = *codePtr;
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rex = *codePtr;
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if (rex & 8) //REX.W
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if (rex & 8) //REX.W
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{
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{
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info.operandSize = 8;
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info->operandSize = 8;
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}
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}
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codePtr++;
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codePtr++;
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}
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}
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@ -85,21 +85,21 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int acc
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if (hasModRM)
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if (hasModRM)
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{
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{
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ModRM mrm(modRMbyte, rex);
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ModRM mrm(modRMbyte, rex);
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info.regOperandReg = mrm.reg;
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info->regOperandReg = mrm.reg;
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if (mrm.mod < 3)
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if (mrm.mod < 3)
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{
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{
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if (mrm.rm == 4)
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if (mrm.rm == 4)
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{
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{
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//SIB byte
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//SIB byte
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sibByte = *codePtr++;
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sibByte = *codePtr++;
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info.scaledReg = (sibByte >> 3) & 7;
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info->scaledReg = (sibByte >> 3) & 7;
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info.otherReg = (sibByte & 7);
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info->otherReg = (sibByte & 7);
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if (rex & 2) info.scaledReg += 8;
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if (rex & 2) info->scaledReg += 8;
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if (rex & 1) info.otherReg += 8;
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if (rex & 1) info->otherReg += 8;
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}
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}
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else
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else
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{
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{
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//info.scaledReg =
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//info->scaledReg =
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}
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}
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}
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}
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if (mrm.mod == 1 || mrm.mod == 2)
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if (mrm.mod == 1 || mrm.mod == 2)
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@ -112,100 +112,103 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int acc
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}
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}
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if (displacementSize == 1)
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if (displacementSize == 1)
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info.displacement = (s32)(s8)*codePtr;
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info->displacement = (s32)(s8)*codePtr;
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else
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else
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info.displacement = *((s32 *)codePtr);
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info->displacement = *((s32 *)codePtr);
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codePtr += displacementSize;
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codePtr += displacementSize;
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if (accessType == 1)
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{
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info.isMemoryWrite = true;
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//Write access
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switch (codeByte)
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switch (codeByte)
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{
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{
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case MOVE_8BIT: //move 8-bit immediate
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// writes
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case 0xC6: // mem <- imm8
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{
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{
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info.hasImmediate = true;
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info->isMemoryWrite = true;
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info.immediate = *codePtr;
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info->hasImmediate = true;
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info->immediate = *codePtr;
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codePtr++; //move past immediate
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codePtr++; //move past immediate
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}
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}
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break;
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break;
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case MOVE_16_32BIT: //move 16 or 32-bit immediate, easiest case for writes
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case 0xC7: // mem <- imm16/32
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{
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{
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if (info.operandSize == 2)
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info->isMemoryWrite = true;
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if (info->operandSize == 2)
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{
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{
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info.hasImmediate = true;
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info->hasImmediate = true;
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info.immediate = *(u16*)codePtr;
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info->immediate = *(u16*)codePtr;
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codePtr += 2;
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codePtr += 2;
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}
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}
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else if (info.operandSize == 4)
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else if (info->operandSize == 4)
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{
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{
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info.hasImmediate = true;
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info->hasImmediate = true;
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info.immediate = *(u32*)codePtr;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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codePtr += 4;
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}
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}
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else if (info.operandSize == 8)
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else if (info->operandSize == 8)
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{
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{
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info.zeroExtend = true;
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info->zeroExtend = true;
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info.immediate = *(u32*)codePtr;
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info->immediate = *(u32*)codePtr;
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codePtr += 4;
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codePtr += 4;
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}
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}
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}
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}
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break;
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case MOVE_REG_TO_MEM: //move reg to memory
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break;
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default:
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case 0x89: // mem <- r16/32/64
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PanicAlert("Unhandled disasm case in write handler!\n\nPlease implement or avoid.");
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return false;
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}
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}
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else
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{
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{
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// Memory read
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info->isMemoryWrite = true;
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break;
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}
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//mov eax, dword ptr [rax] == 8b 00
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case 0x0F: // two-byte escape
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switch (codeByte)
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{
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{
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case 0x0F:
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info->isMemoryWrite = false;
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switch (codeByte2)
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switch (codeByte2)
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{
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{
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case MOVZX_BYTE: //movzx on byte
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case 0xB6: // movzx on byte
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info.zeroExtend = true;
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info->zeroExtend = true;
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info.operandSize = 1;
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info->operandSize = 1;
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break;
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break;
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case MOVZX_SHORT: //movzx on short
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case 0xB7: // movzx on short
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info.zeroExtend = true;
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info->zeroExtend = true;
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info.operandSize = 2;
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info->operandSize = 2;
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break;
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break;
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case MOVSX_BYTE: //movsx on byte
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case 0xBE: // movsx on byte
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info.signExtend = true;
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info->signExtend = true;
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info.operandSize = 1;
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info->operandSize = 1;
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break;
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break;
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case MOVSX_SHORT: //movsx on short
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case 0xBF: // movsx on short
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info.signExtend = true;
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info->signExtend = true;
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info.operandSize = 2;
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info->operandSize = 2;
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break;
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break;
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default:
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default:
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return false;
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return false;
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}
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}
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break;
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break;
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case 0x8a:
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}
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if (info.operandSize == 4)
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case 0x8A: // r8 <- mem
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{
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{
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info.operandSize = 1;
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info->isMemoryWrite = false;
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if (info->operandSize == 4)
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{
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info->operandSize = 1;
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break;
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break;
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}
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}
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else
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else
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return false;
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return false;
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case 0x8b:
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}
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break; //it's OK don't need to do anything
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case 0x8B: // r16/32/64 <- mem
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{
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info->isMemoryWrite = false;
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break;
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}
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break;
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default:
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default:
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return false;
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return false;
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}
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}
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}
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info->instructionSize = (int)(codePtr - startCodePtr);
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info.instructionSize = (int)(codePtr - startCodePtr);
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return true;
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return true;
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}
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}
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@ -33,21 +33,12 @@ struct ModRM
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}
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}
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};
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};
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enum{
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enum AccessType
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MOVZX_BYTE = 0xB6, //movzx on byte
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{
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MOVZX_SHORT = 0xB7, //movzx on short
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MOVSX_BYTE = 0xBE, //movsx on byte
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MOVSX_SHORT = 0xBF, //movsx on short
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MOVE_8BIT = 0xC6, //move 8-bit immediate
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MOVE_16_32BIT = 0xC7, //move 16 or 32-bit immediate
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MOVE_REG_TO_MEM = 0x89, //move reg to memory
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};
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enum AccessType{
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OP_ACCESS_READ = 0,
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OP_ACCESS_READ = 0,
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OP_ACCESS_WRITE = 1
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OP_ACCESS_WRITE = 1
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};
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};
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bool DisassembleMov(const unsigned char *codePtr, InstructionInfo &info, int accessType);
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bool DisassembleMov(const unsigned char *codePtr, InstructionInfo *info);
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#endif // _X64ANALYZER_H_
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#endif // _X64ANALYZER_H_
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@ -81,11 +81,9 @@ void sigsegv_handler(int signal, siginfo_t *info, void *raw_context)
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u32 em_address = (u32)(bad_address - memspace_bottom);
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u32 em_address = (u32)(bad_address - memspace_bottom);
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int access_type = 0;
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CONTEXT fake_ctx;
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CONTEXT fake_ctx;
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fake_ctx.reg_pc = ctx->arm_pc;
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fake_ctx.reg_pc = ctx->arm_pc;
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const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, access_type, em_address, &fake_ctx);
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const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, em_address, &fake_ctx);
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if (new_rip) {
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if (new_rip) {
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ctx->arm_pc = fake_ctx.reg_pc;
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ctx->arm_pc = fake_ctx.reg_pc;
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}
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}
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@ -96,7 +96,7 @@ bool DisamLoadStore(const u32 inst, ARMReg &rD, u8 &accessSize, bool &Store)
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}
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}
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return true;
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return true;
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}
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}
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const u8 *JitArm::BackPatch(u8 *codePtr, int accessType, u32 emAddress, void *ctx_void)
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const u8 *JitArm::BackPatch(u8 *codePtr, u32 emAddress, void *ctx_void)
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{
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{
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// TODO: This ctx needs to be filled with our information
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// TODO: This ctx needs to be filled with our information
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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@ -160,7 +160,7 @@ const u8 *TrampolineCache::GetWriteTrampoline(const InstructionInfo &info)
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// 1) It's really necessary. We don't know anything about the context.
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// 1) It's really necessary. We don't know anything about the context.
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// 2) It doesn't really hurt. Only instructions that access I/O will get these, and there won't be
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// 2) It doesn't really hurt. Only instructions that access I/O will get these, and there won't be
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// that many of them in a typical program/game.
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// that many of them in a typical program/game.
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const u8 *Jitx86Base::BackPatch(u8 *codePtr, int accessType, u32 emAddress, void *ctx_void)
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const u8 *Jitx86Base::BackPatch(u8 *codePtr, u32 emAddress, void *ctx_void)
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{
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{
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#ifdef _M_X64
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#ifdef _M_X64
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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CONTEXT *ctx = (CONTEXT *)ctx_void;
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@ -169,29 +169,15 @@ const u8 *Jitx86Base::BackPatch(u8 *codePtr, int accessType, u32 emAddress, void
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return 0; // this will become a regular crash real soon after this
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return 0; // this will become a regular crash real soon after this
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InstructionInfo info;
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InstructionInfo info;
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if (!DisassembleMov(codePtr, info, accessType)) {
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if (!DisassembleMov(codePtr, &info)) {
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BackPatchError("BackPatch - failed to disassemble MOV instruction", codePtr, emAddress);
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BackPatchError("BackPatch - failed to disassemble MOV instruction", codePtr, emAddress);
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}
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}
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/*
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if (info.isMemoryWrite) {
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if (!Memory::IsRAMAddress(emAddress, true)) {
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PanicAlert("Exception: Caught write to invalid address %08x", emAddress);
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return;
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}
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BackPatchError("BackPatch - determined that MOV is write, not yet supported and should have been caught before",
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codePtr, emAddress);
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}*/
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if (info.otherReg != RBX)
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if (info.otherReg != RBX)
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PanicAlert("BackPatch : Base reg not RBX."
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PanicAlert("BackPatch : Base reg not RBX."
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"\n\nAttempted to access %08x.", emAddress);
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"\n\nAttempted to access %08x.", emAddress);
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if (accessType == OP_ACCESS_WRITE)
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if (!info.isMemoryWrite)
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PanicAlert("BackPatch : Currently only supporting reads."
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"\n\nAttempted to write to %08x.", emAddress);
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if (accessType == 0)
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{
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{
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XEmitter emitter(codePtr);
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XEmitter emitter(codePtr);
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int bswapNopCount;
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int bswapNopCount;
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@ -205,8 +191,11 @@ const u8 *Jitx86Base::BackPatch(u8 *codePtr, int accessType, u32 emAddress, void
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emitter.NOP((int)info.instructionSize + bswapNopCount - 5);
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emitter.NOP((int)info.instructionSize + bswapNopCount - 5);
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return codePtr;
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return codePtr;
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}
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}
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else if (accessType == 1)
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else
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{
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{
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PanicAlert("BackPatch : Currently only supporting reads."
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"\n\nAttempted to write to %08x.", emAddress);
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// TODO: special case FIFO writes. Also, support 32-bit mode.
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// TODO: special case FIFO writes. Also, support 32-bit mode.
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// Also, debug this so that it actually works correctly :P
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// Also, debug this so that it actually works correctly :P
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XEmitter emitter(codePtr - 2);
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XEmitter emitter(codePtr - 2);
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@ -74,7 +74,7 @@ public:
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virtual void Jit(u32 em_address) = 0;
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virtual void Jit(u32 em_address) = 0;
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virtual const u8 *BackPatch(u8 *codePtr, int accessType, u32 em_address, void *ctx) = 0;
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virtual const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx) = 0;
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virtual const CommonAsmRoutinesBase *GetAsmRoutines() = 0;
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virtual const CommonAsmRoutinesBase *GetAsmRoutines() = 0;
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@ -89,7 +89,7 @@ protected:
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public:
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public:
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JitBlockCache *GetBlockCache() { return &blocks; }
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JitBlockCache *GetBlockCache() { return &blocks; }
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const u8 *BackPatch(u8 *codePtr, int accessType, u32 em_address, void *ctx);
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const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx);
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bool IsInCodeSpace(u8 *ptr) { return IsInSpace(ptr); }
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bool IsInCodeSpace(u8 *ptr) { return IsInSpace(ptr); }
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};
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};
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@ -175,9 +175,9 @@ namespace JitInterface
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{
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{
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return jit->IsInCodeSpace(ptr);
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return jit->IsInCodeSpace(ptr);
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}
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}
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const u8 *BackPatch(u8 *codePtr, int accessType, u32 em_address, void *ctx)
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const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx)
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{
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{
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return jit->BackPatch(codePtr, accessType, em_address, ctx);
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return jit->BackPatch(codePtr, em_address, ctx);
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}
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}
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void ClearCache()
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void ClearCache()
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@ -18,7 +18,7 @@ namespace JitInterface
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// Memory Utilities
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// Memory Utilities
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bool IsInCodeSpace(u8 *ptr);
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bool IsInCodeSpace(u8 *ptr);
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const u8 *BackPatch(u8 *codePtr, int accessType, u32 em_address, void *ctx);
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const u8 *BackPatch(u8 *codePtr, u32 em_address, void *ctx);
|
||||||
|
|
||||||
// used by JIT to read instructions
|
// used by JIT to read instructions
|
||||||
u32 Read_Opcode_JIT(const u32 _Address);
|
u32 Read_Opcode_JIT(const u32 _Address);
|
||||||
|
|
|
@ -99,7 +99,7 @@ LONG NTAPI Handler(PEXCEPTION_POINTERS pPtrs)
|
||||||
|
|
||||||
//We could emulate the memory accesses here, but then they would still be around to take up
|
//We could emulate the memory accesses here, but then they would still be around to take up
|
||||||
//execution resources. Instead, we backpatch into a generic memory call and retry.
|
//execution resources. Instead, we backpatch into a generic memory call and retry.
|
||||||
const u8 *new_rip = JitInterface::BackPatch(codePtr, accessType, emAddress, ctx);
|
const u8 *new_rip = JitInterface::BackPatch(codePtr, emAddress, ctx);
|
||||||
|
|
||||||
// Rip/Eip needs to be updated.
|
// Rip/Eip needs to be updated.
|
||||||
if (new_rip)
|
if (new_rip)
|
||||||
|
@ -214,7 +214,6 @@ void sigsegv_handler(int signal, siginfo_t *info, void *raw_context)
|
||||||
// Backpatch time.
|
// Backpatch time.
|
||||||
// Seems we'll need to disassemble to get access_type - that work is probably
|
// Seems we'll need to disassemble to get access_type - that work is probably
|
||||||
// best done and debugged on the Windows side.
|
// best done and debugged on the Windows side.
|
||||||
int access_type = 0;
|
|
||||||
|
|
||||||
CONTEXT fake_ctx;
|
CONTEXT fake_ctx;
|
||||||
|
|
||||||
|
@ -225,7 +224,7 @@ void sigsegv_handler(int signal, siginfo_t *info, void *raw_context)
|
||||||
fake_ctx.Eax = CREG_EAX(ctx);
|
fake_ctx.Eax = CREG_EAX(ctx);
|
||||||
fake_ctx.Eip = CREG_EIP(ctx);
|
fake_ctx.Eip = CREG_EIP(ctx);
|
||||||
#endif
|
#endif
|
||||||
const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, access_type, em_address, &fake_ctx);
|
const u8 *new_rip = jit->BackPatch(fault_instruction_ptr, em_address, &fake_ctx);
|
||||||
if (new_rip)
|
if (new_rip)
|
||||||
{
|
{
|
||||||
#ifdef _M_X64
|
#ifdef _M_X64
|
||||||
|
|
Loading…
Reference in New Issue