From 49eeb986c6c943dd4a21c28c6627a4a94c8cf40a Mon Sep 17 00:00:00 2001 From: "Admiral H. Curtiss" Date: Mon, 9 Jan 2023 20:47:18 +0100 Subject: [PATCH] PowerPC: Parametrize HID0 macro. --- Source/Core/Core/Boot/Boot_BS2Emu.cpp | 18 +++++++++--------- .../Interpreter/Interpreter_LoadStore.cpp | 4 ++-- .../Interpreter_SystemRegisters.cpp | 16 +++++++++------- Source/Core/Core/PowerPC/MMU.cpp | 11 +++++++---- Source/Core/Core/PowerPC/PPCCache.cpp | 6 +++--- Source/Core/Core/PowerPC/PowerPC.h | 2 +- 6 files changed, 31 insertions(+), 26 deletions(-) diff --git a/Source/Core/Core/Boot/Boot_BS2Emu.cpp b/Source/Core/Core/Boot/Boot_BS2Emu.cpp index 5c5cece792..f9722923ff 100644 --- a/Source/Core/Core/Boot/Boot_BS2Emu.cpp +++ b/Source/Core/Core/Boot/Boot_BS2Emu.cpp @@ -76,18 +76,18 @@ void CBoot::SetupMSR() void CBoot::SetupHID(bool is_wii) { // HID0 is 0x0011c464 on GC, 0x0011c664 on Wii - HID0.BHT = 1; - HID0.BTIC = 1; - HID0.DCFA = 1; + HID0(PowerPC::ppcState).BHT = 1; + HID0(PowerPC::ppcState).BTIC = 1; + HID0(PowerPC::ppcState).DCFA = 1; if (is_wii) - HID0.SPD = 1; - HID0.DCFI = 1; - HID0.DCE = 1; + HID0(PowerPC::ppcState).SPD = 1; + HID0(PowerPC::ppcState).DCFI = 1; + HID0(PowerPC::ppcState).DCE = 1; // Note that Datel titles will fail to boot if the instruction cache is not enabled; see // https://bugs.dolphin-emu.org/issues/8223 - HID0.ICE = 1; - HID0.NHR = 1; - HID0.DPM = 1; + HID0(PowerPC::ppcState).ICE = 1; + HID0(PowerPC::ppcState).NHR = 1; + HID0(PowerPC::ppcState).DPM = 1; // HID1 is initialized in PowerPC.cpp to 0x80000000 // HID2 is 0xe0000000 diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp index 1c1a341c85..e436a67a04 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp @@ -503,7 +503,7 @@ void Interpreter::dcbz(UGeckoInstruction inst) { const u32 dcbz_addr = Helper_Get_EA_X(PowerPC::ppcState, inst); - if (!HID0.DCE) + if (!HID0(PowerPC::ppcState).DCE) { GenerateAlignmentException(dcbz_addr); return; @@ -533,7 +533,7 @@ void Interpreter::dcbz_l(UGeckoInstruction inst) const u32 address = Helper_Get_EA_X(PowerPC::ppcState, inst); - if (!HID0.DCE) + if (!HID0(PowerPC::ppcState).DCE) { GenerateAlignmentException(address); return; diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index f96cf4ffc7..9454a14fc3 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -325,18 +325,20 @@ void Interpreter::mtspr(UGeckoInstruction inst) { UReg_HID0 old_hid0; old_hid0.Hex = old_value; - if (HID0.ICE != old_hid0.ICE) + if (HID0(PowerPC::ppcState).ICE != old_hid0.ICE) { - INFO_LOG_FMT(POWERPC, "Instruction Cache Enable (HID0.ICE) = {}", HID0.ICE); + INFO_LOG_FMT(POWERPC, "Instruction Cache Enable (HID0.ICE) = {}", + HID0(PowerPC::ppcState).ICE); } - if (HID0.ILOCK != old_hid0.ILOCK) + if (HID0(PowerPC::ppcState).ILOCK != old_hid0.ILOCK) { - INFO_LOG_FMT(POWERPC, "Instruction Cache Lock (HID0.ILOCK) = {}", HID0.ILOCK); + INFO_LOG_FMT(POWERPC, "Instruction Cache Lock (HID0.ILOCK) = {}", + HID0(PowerPC::ppcState).ILOCK); } - if (HID0.ICFI) + if (HID0(PowerPC::ppcState).ICFI) { - HID0.ICFI = 0; - INFO_LOG_FMT(POWERPC, "Flush Instruction Cache! ICE={}", HID0.ICE); + HID0(PowerPC::ppcState).ICFI = 0; + INFO_LOG_FMT(POWERPC, "Flush Instruction Cache! ICE={}", HID0(PowerPC::ppcState).ICE); // this is rather slow // most games do it only once during initialization PowerPC::ppcState.iCache.Reset(); diff --git a/Source/Core/Core/PowerPC/MMU.cpp b/Source/Core/Core/PowerPC/MMU.cpp index 98d6a45b01..8a356cf00b 100644 --- a/Source/Core/Core/PowerPC/MMU.cpp +++ b/Source/Core/Core/PowerPC/MMU.cpp @@ -235,7 +235,7 @@ static T ReadFromHardware(Memory::MemoryManager& memory, u32 em_address) else { ppcState.dCache.Read(em_address, &value, sizeof(T), - HID0.DLOCK || flag != XCheckTLBFlag::Read); + HID0(PowerPC::ppcState).DLOCK || flag != XCheckTLBFlag::Read); } return bswap(value); @@ -254,7 +254,7 @@ static T ReadFromHardware(Memory::MemoryManager& memory, u32 em_address) else { ppcState.dCache.Read(em_address + 0x10000000, &value, sizeof(T), - HID0.DLOCK || flag != XCheckTLBFlag::Read); + HID0(PowerPC::ppcState).DLOCK || flag != XCheckTLBFlag::Read); } return bswap(value); @@ -425,7 +425,7 @@ static void WriteToHardware(Core::System& system, Memory::MemoryManager& memory, em_address &= memory.GetRamMask(); if (ppcState.m_enable_dcache && !wi) - ppcState.dCache.Write(em_address, &swapped_data, size, HID0.DLOCK); + ppcState.dCache.Write(em_address, &swapped_data, size, HID0(PowerPC::ppcState).DLOCK); if (!ppcState.m_enable_dcache || wi || flag != XCheckTLBFlag::Write) std::memcpy(&memory.GetRAM()[em_address], &swapped_data, size); @@ -439,7 +439,10 @@ static void WriteToHardware(Core::System& system, Memory::MemoryManager& memory, em_address &= 0x0FFFFFFF; if (ppcState.m_enable_dcache && !wi) - ppcState.dCache.Write(em_address + 0x10000000, &swapped_data, size, HID0.DLOCK); + { + ppcState.dCache.Write(em_address + 0x10000000, &swapped_data, size, + HID0(PowerPC::ppcState).DLOCK); + } if (!ppcState.m_enable_dcache || wi || flag != XCheckTLBFlag::Write) std::memcpy(&memory.GetEXRAM()[em_address], &swapped_data, size); diff --git a/Source/Core/Core/PowerPC/PPCCache.cpp b/Source/Core/Core/PowerPC/PPCCache.cpp index d56d77927c..de1b214e29 100644 --- a/Source/Core/Core/PowerPC/PPCCache.cpp +++ b/Source/Core/Core/PowerPC/PPCCache.cpp @@ -394,17 +394,17 @@ u32 InstructionCache::ReadInstruction(u32 addr) auto& system = Core::System::GetInstance(); auto& memory = system.GetMemory(); - if (!HID0.ICE || m_disable_icache) // instruction cache is disabled + if (!HID0(PowerPC::ppcState).ICE || m_disable_icache) // instruction cache is disabled return memory.Read_U32(addr); u32 value; - Read(addr, &value, sizeof(value), HID0.ILOCK); + Read(addr, &value, sizeof(value), HID0(PowerPC::ppcState).ILOCK); return Common::swap32(value); } void InstructionCache::Invalidate(u32 addr) { - if (!HID0.ICE || m_disable_icache) + if (!HID0(PowerPC::ppcState).ICE || m_disable_icache) return; // Invalidates the whole set diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h index 4d70ab7439..e5fc426f69 100644 --- a/Source/Core/Core/PowerPC/PowerPC.h +++ b/Source/Core/Core/PowerPC/PowerPC.h @@ -235,7 +235,7 @@ void WriteFullTimeBaseValue(u64 value); void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst); // Easy register access macros. -#define HID0 ((UReg_HID0&)PowerPC::ppcState.spr[SPR_HID0]) +#define HID0(ppc_state) ((UReg_HID0&)(ppc_state).spr[SPR_HID0]) #define HID2 ((UReg_HID2&)PowerPC::ppcState.spr[SPR_HID2]) #define HID4 ((UReg_HID4&)PowerPC::ppcState.spr[SPR_HID4]) #define DMAU (*(UReg_DMAU*)&PowerPC::ppcState.spr[SPR_DMAU])