DSP LLE Jit, joined work with XK and skidu.
VERY EXPERIMENTAL DON'T EXPECT HIGH PERFORMANCE!. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5288 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
1b96bef8e1
commit
499936561a
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@ -157,8 +157,7 @@ void AICallback(u64 userdata, int cyclesLate)
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// DSP/CPU timeslicing.
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void DSPCallback(u64 userdata, int cyclesLate)
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{
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// ~1/6th as many cycles as the period PPC-side.
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CPluginManager::GetInstance().GetDSP()->DSP_Update(DSP_PERIOD / 6);
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CPluginManager::GetInstance().GetDSP()->DSP_Update(DSP_PERIOD + cyclesLate);
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CoreTiming::ScheduleEvent(DSP_PERIOD - cyclesLate, et_DSP);
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}
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@ -523,11 +523,11 @@
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>
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</File>
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<File
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RelativePath=".\Src\DSPJit.cpp"
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RelativePath=".\Src\DSPEmitter.cpp"
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>
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</File>
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<File
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RelativePath=".\Src\DSPJit.h"
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RelativePath=".\Src\DSPEmitter.h"
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>
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</File>
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<File
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@ -0,0 +1,8 @@
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#ifndef __DSPCOMMON_H
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#define __DSPCOMMON_H
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#include "CommonTypes.h"
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typedef u16 UDSPInstruction;
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#endif
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@ -26,6 +26,7 @@
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#include "Common.h"
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#include "Thread.h"
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#include "DSPCore.h"
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#include "DSPEmitter.h"
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#include "DSPHost.h"
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#include "DSPAnalyzer.h"
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#include "MemoryUtil.h"
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@ -36,6 +37,7 @@
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SDSP g_dsp;
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DSPBreakpoints dsp_breakpoints;
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DSPCoreState core_state = DSPCORE_RUNNING;
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DSPEmitter *jit = NULL;
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Common::Event step_event;
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static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
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@ -65,10 +67,12 @@ static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
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return false;
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}
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename,
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bool bUsingJIT)
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{
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g_dsp.step_counter = 0;
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jit = NULL;
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g_dsp.irom = (u16*)AllocateMemoryPages(DSP_IROM_BYTE_SIZE);
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g_dsp.iram = (u16*)AllocateMemoryPages(DSP_IRAM_BYTE_SIZE);
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g_dsp.dram = (u16*)AllocateMemoryPages(DSP_DRAM_BYTE_SIZE);
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@ -124,7 +128,13 @@ bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
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// Mostly keep IRAM write protected. We unprotect only when DMA-ing
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// in new ucodes.
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WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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// Initialize JIT, if necessary
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if(bUsingJIT)
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jit = new DSPEmitter();
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DSPAnalyzer::Analyze();
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step_event.Init();
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return true;
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@ -132,6 +142,10 @@ bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
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void DSPCore_Shutdown()
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{
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if(jit) {
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delete jit;
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jit = NULL;
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}
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step_event.Shutdown();
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FreeMemoryPages(g_dsp.irom, DSP_IROM_BYTE_SIZE);
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FreeMemoryPages(g_dsp.iram, DSP_IRAM_BYTE_SIZE);
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@ -214,10 +228,14 @@ void DSPCore_CheckExceptions()
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}
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}
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// Delegate to JIT (when it is written) or interpreter as appropriate.
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// Delegate to JIT or interpreter as appropriate.
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// Handle state changes and stepping.
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int DSPCore_RunCycles(int cycles)
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{
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if(jit) {
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jit->RunBlock(cycles);
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return 0;
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}
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while (cycles > 0) {
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reswitch:
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switch (core_state)
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@ -266,3 +284,8 @@ void DSPCore_Step()
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if (core_state == DSPCORE_STEPPING)
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step_event.Set();
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}
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void CompileCurrent() {
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jit->Compile(g_dsp.pc);
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}
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@ -29,6 +29,7 @@
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#include "Thread.h"
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#include "DSPBreakpoints.h"
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#include "DSPEmitter.h"
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#define DSP_IRAM_BYTE_SIZE 0x2000
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#define DSP_IRAM_SIZE 0x1000
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@ -233,8 +234,10 @@ struct SDSP
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extern SDSP g_dsp;
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extern DSPBreakpoints dsp_breakpoints;
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extern DSPEmitter *jit;
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename);
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename,
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bool bUsingJIT);
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void DSPCore_Reset();
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void DSPCore_Shutdown(); // Frees all allocated memory.
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@ -245,6 +248,8 @@ void DSPCore_CheckExceptions();
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// sets a flag in the pending exception register.
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void DSPCore_SetException(u8 level);
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void CompileCurrent();
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enum DSPCoreState
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{
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DSPCORE_RUNNING = 0,
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@ -0,0 +1,231 @@
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// Copyright (C) 2010 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include <cstring>
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#include "DSPEmitter.h"
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#include "DSPMemoryMap.h"
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#include "DSPCore.h"
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#include "DSPInterpreter.h"
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#include "DSPAnalyzer.h"
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#include "x64Emitter.h"
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#include "ABI.h"
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#define BLOCK_SIZE 250
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using namespace Gen;
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DSPEmitter::DSPEmitter()
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{
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m_compiledCode = NULL;
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AllocCodeSpace(COMPILED_CODE_SIZE);
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blocks = new CompiledCode[MAX_BLOCKS];
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endBlock = new bool[MAX_BLOCKS];
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for(int i = 0x0000; i < MAX_BLOCKS; i++)
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{
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blocks[i] = CompileCurrent;
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blockSize[i] = 0;
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endBlock[i] = false;
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}
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}
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DSPEmitter::~DSPEmitter()
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{
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delete[] blocks;
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delete[] endBlock;
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FreeCodeSpace();
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}
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void DSPEmitter::ClearIRAM() {
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// TODO: Does not clear codespace
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for(int i = 0x0000; i < 0x1000; i++)
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{
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blocks[i] = CompileCurrent;
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blockSize[i] = 0;
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endBlock[i] = false;
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}
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}
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void DSPEmitter::WriteCallInterpreter(UDSPInstruction inst)
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{
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const DSPOPCTemplate *tinst = GetOpTemplate(inst);
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// Call extended
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if (tinst->extended) {
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if ((inst >> 12) == 0x3) {
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if (! extOpTable[inst & 0x7F]->jitFunc) {
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ABI_CallFunctionC16((void*)extOpTable[inst & 0x7F]->intFunc, inst);
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} else {
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(this->*extOpTable[inst & 0x7F]->jitFunc)(inst);
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}
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} else {
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if (!extOpTable[inst & 0xFF]->jitFunc) {
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ABI_CallFunctionC16((void*)extOpTable[inst & 0xFF]->intFunc, inst);
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} else {
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(this->*extOpTable[inst & 0xFF]->jitFunc)(inst);
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}
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}
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}
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// Main instruction
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if (!opTable[inst]->jitFunc)
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ABI_CallFunctionC16((void*)opTable[inst]->intFunc, inst);
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else
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(this->*opTable[inst]->jitFunc)(inst);
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// Backlog
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// TODO if for jit
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if (tinst->extended) {
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ABI_CallFunction((void*)applyWriteBackLog);
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}
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}
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void DSPEmitter::unknown_instruction(UDSPInstruction inst)
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{
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PanicAlert("unknown_instruction %04x - Fix me ;)", inst);
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}
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void DSPEmitter::Default(UDSPInstruction _inst)
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{
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WriteCallInterpreter(_inst);
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}
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const u8 *DSPEmitter::Compile(int start_addr) {
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AlignCode16();
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const u8 *entryPoint = GetCodePtr();
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ABI_PushAllCalleeSavedRegsAndAdjustStack();
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int addr = start_addr;
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while (addr < start_addr + BLOCK_SIZE)
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{
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UDSPInstruction inst = dsp_imem_read(addr);
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const DSPOPCTemplate *opcode = GetOpTemplate(inst);
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// Check for interrupts and exceptions
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TEST(8, M(&g_dsp.exceptions), Imm8(0xff));
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FixupBranch skipCheck = J_CC(CC_Z);
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ABI_CallFunction((void *)&DSPCore_CheckExceptions);
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MOV(32, R(EAX), M(&g_dsp.exception_in_progress));
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CMP(32, R(EAX), Imm32(0));
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FixupBranch noExceptionOccurred = J_CC(CC_L);
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ABI_CallFunction((void *)DSPInterpreter::HandleLoop);
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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SetJumpTarget(skipCheck);
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SetJumpTarget(noExceptionOccurred);
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// Increment PC
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ADD(16, M(&(g_dsp.pc)), Imm16(1));
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WriteCallInterpreter(inst);
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blockSize[start_addr]++;
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// Handle loop condition. Change to TEST
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MOVZX(32, 16, EAX, M(&(g_dsp.r[DSP_REG_ST2])));
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CMP(32, R(EAX), Imm32(0));
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FixupBranch rLoopAddressExit = J_CC(CC_LE);
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MOVZX(32, 16, EAX, M(&(g_dsp.r[DSP_REG_ST3])));
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CMP(32, R(EAX), Imm32(0));
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FixupBranch rLoopCounterExit = J_CC(CC_LE);
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// These functions branch and therefore only need to be called in the end
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// of each block and in this order
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ABI_CallFunction((void *)&DSPInterpreter::HandleLoop);
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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SetJumpTarget(rLoopAddressExit);
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SetJumpTarget(rLoopCounterExit);
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// End the block where the loop ends
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if ((inst & 0xffe0) == 0x0060 || (inst & 0xff00) == 0x1100) {
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// BLOOP, BLOOPI
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endBlock[dsp_imem_read(addr + 1)] = true;
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} else if ((inst & 0xffe0) == 0x0040 || (inst & 0xff00) == 0x1000) {
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// LOOP, LOOPI
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endBlock[addr + 1] = true;
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}
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if (opcode->branch || endBlock[addr]
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|| DSPAnalyzer::code_flags[addr] & DSPAnalyzer::CODE_IDLE_SKIP)
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break;
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addr += opcode->size;
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}
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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blocks[start_addr] = (CompiledCode)entryPoint;
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return entryPoint;
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}
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void STACKALIGN DSPEmitter::RunBlock(int cycles)
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{
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static int idleskip = 0;
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// Trigger an external interrupt at the start of the cycle
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u16 block_cycles = 501;
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while (!(g_dsp.cr & CR_HALT))
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{
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if (block_cycles > 500)
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{
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if(g_dsp.cr & CR_EXTERNAL_INT)
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DSPCore_CheckExternalInterrupt();
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block_cycles = 0;
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}
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// Compile the block if needed
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if (blocks[g_dsp.pc] == CompileCurrent)
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{
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blockSize[g_dsp.pc] = 0;
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blocks[g_dsp.pc]();
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}
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// Execute the block if we have enough cycles
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if (cycles > blockSize[g_dsp.pc])
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{
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u16 start_addr = g_dsp.pc;
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if (idleskip % 100 > 95 && (DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)) {
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block_cycles = 0;
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} else
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blocks[g_dsp.pc]();
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idleskip++;
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if (idleskip % 500 == 0)
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idleskip = 0;
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block_cycles += blockSize[start_addr];
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cycles -= blockSize[start_addr];
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}
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else {
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break;
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}
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}
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}
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@ -0,0 +1,86 @@
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _DSPEMITTER_H
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#define _DSPEMITTER_H
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#include "DSPCommon.h"
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#include "x64Emitter.h"
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#define COMPILED_CODE_SIZE sizeof(void *) * 0x200000
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#define MAX_BLOCKS 0x10000
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typedef void (*CompiledCode)();
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class DSPEmitter : public Gen::XCodeBlock
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{
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CompiledCode *blocks;
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u16 blockSize[0x10000];
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bool *endBlock;
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public:
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DSPEmitter();
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~DSPEmitter();
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const u8 *m_compiledCode;
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void WriteCallInterpreter(UDSPInstruction inst);
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void unknown_instruction(UDSPInstruction inst);
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void Default(UDSPInstruction _inst);
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void ClearIRAM();
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const u8 *Compile(int start_addr);
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void STACKALIGN RunBlock(int cycles);
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DISALLOW_COPY_AND_ASSIGN(DSPEmitter);
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// Memory helper functions
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void increment_addr_reg(int reg);
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void decrement_addr_reg(int reg);
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void increase_addr_reg(int reg);
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void decrease_addr_reg(int reg);
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void ext_dmem_write(u32 src, u32 dest);
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u16 ext_dmem_read(u16 addr);
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void writeAxAcc(const UDSPInstruction opc);
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// Ext commands
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void l(const UDSPInstruction opc);
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void ln(const UDSPInstruction opc);
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void ls(const UDSPInstruction opc);
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void lsn(const UDSPInstruction opc);
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void lsm(const UDSPInstruction opc);
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void lsnm(const UDSPInstruction opc);
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void sl(const UDSPInstruction opc);
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void sln(const UDSPInstruction opc);
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void slm(const UDSPInstruction opc);
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void slnm(const UDSPInstruction opc);
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void s(const UDSPInstruction opc);
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void sn(const UDSPInstruction opc);
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void ld(const UDSPInstruction opc);
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void ldn(const UDSPInstruction opc);
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void ldm(const UDSPInstruction opc);
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void ldnm(const UDSPInstruction opc);
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void mv(const UDSPInstruction opc);
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void dr(const UDSPInstruction opc);
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void ir(const UDSPInstruction opc);
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void nr(const UDSPInstruction opc);
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void nop(const UDSPInstruction opc) {}
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};
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#endif // _DSPEMITTER_H
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@ -133,7 +133,7 @@ void gdsp_ifx_write(u16 addr, u16 val)
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if (val & 0x1)
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DSPHost_InterruptRequest();
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else
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INFO_LOG(DSPLLE, "Unknown Interrupt Request pc=%04x (%04x)", g_dsp.pc, val);
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WARN_LOG(DSPLLE, "Unknown Interrupt Request pc=%04x (%04x)", g_dsp.pc, val);
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break;
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case DSP_DMBH:
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|
|
@ -254,6 +254,9 @@ void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
|
|||
|
||||
NOTICE_LOG(DSPLLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)", addr, dsp_addr, g_dsp.iram_crc);
|
||||
|
||||
if (jit)
|
||||
jit->ClearIRAM();
|
||||
|
||||
DSPAnalyzer::Analyze();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -103,19 +103,23 @@ void Run()
|
|||
int checkInterrupt = 0;
|
||||
gdsp_running = true;
|
||||
while (!(g_dsp.cr & CR_HALT) && gdsp_running)
|
||||
{
|
||||
// Automatically let the other threads work if we're idle skipping
|
||||
if(DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)
|
||||
Common::YieldCPU();
|
||||
|
||||
Step();
|
||||
|
||||
// Turns out the less you check for external interrupts, the more
|
||||
// sound you hear, and it becomes slower
|
||||
checkInterrupt++;
|
||||
if(checkInterrupt == 500) { // <-- A completely arbitrary number. TODO: tweak
|
||||
DSPCore_CheckExternalInterrupt();
|
||||
checkInterrupt = 0;
|
||||
{
|
||||
if(jit)
|
||||
jit->RunBlock(1);
|
||||
else {
|
||||
// Automatically let the other threads work if we're idle skipping
|
||||
if(DSPAnalyzer::code_flags[g_dsp.pc] & DSPAnalyzer::CODE_IDLE_SKIP)
|
||||
Common::YieldCPU();
|
||||
|
||||
Step();
|
||||
|
||||
// Turns out the less you check for external interrupts, the more
|
||||
// sound you hear, and it becomes slower
|
||||
checkInterrupt++;
|
||||
if(checkInterrupt == 500) { // <-- Arbitrary number. TODO: tweak
|
||||
DSPCore_CheckExternalInterrupt();
|
||||
checkInterrupt = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
gdsp_running = false;
|
||||
|
|
@ -185,7 +189,8 @@ int RunCyclesDebug(int cycles)
|
|||
// Used by non-thread mode. Meant to be efficient.
|
||||
int RunCycles(int cycles)
|
||||
{
|
||||
// First, let's run a few cycles with no idle skipping so that things can progress a bit.
|
||||
// First, let's run a few cycles with no idle skipping so that things can
|
||||
// progress a bit.
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (g_dsp.cr & CR_HALT)
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
// Copyright (C) 2003 Dolphin Project.
|
||||
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, version 2.0.
|
||||
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License 2.0 for more details.
|
||||
|
||||
// A copy of the GPL 2.0 should have been included with the program.
|
||||
// If not, see http://www.gnu.org/licenses/
|
||||
|
||||
// Official SVN repository and contact information can be found at
|
||||
// http://code.google.com/p/dolphin-emu/
|
||||
|
||||
#include "DSPJit.h"
|
||||
|
||||
namespace DSPJit {
|
||||
|
||||
};
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
// Copyright (C) 2003 Dolphin Project.
|
||||
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, version 2.0.
|
||||
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License 2.0 for more details.
|
||||
|
||||
// A copy of the GPL 2.0 should have been included with the program.
|
||||
// If not, see http://www.gnu.org/licenses/
|
||||
|
||||
// Official SVN repository and contact information can be found at
|
||||
// http://code.google.com/p/dolphin-emu/
|
||||
|
||||
#ifndef _DSPJIT_H
|
||||
#define _DSPJIT_H
|
||||
|
||||
namespace DSPJit {
|
||||
|
||||
// TODO(XK): Fill
|
||||
|
||||
|
||||
} // namespace
|
||||
|
||||
#endif // _DSPJIT_H
|
||||
|
|
@ -37,6 +37,7 @@ u16 dsp_dmem_read(u16 addr);
|
|||
inline u16 dsp_fetch_code()
|
||||
{
|
||||
u16 opc = dsp_imem_read(g_dsp.pc);
|
||||
|
||||
g_dsp.pc++;
|
||||
return opc;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include "DSPInterpreter.h"
|
||||
#include "DSPIntExtOps.h"
|
||||
#include "DSPEmitter.h"
|
||||
|
||||
void nop(const UDSPInstruction opc)
|
||||
{
|
||||
|
|
@ -32,305 +33,305 @@ void nop(const UDSPInstruction opc)
|
|||
|
||||
const DSPOPCTemplate opcodes[] =
|
||||
{
|
||||
{"NOP", 0x0000, 0xfffc, nop, nop, 1, 0, {}, false, false},
|
||||
{"NOP", 0x0000, 0xfffc, nop, &DSPEmitter::nop, 1, 0, {}, false, false},
|
||||
|
||||
{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false},
|
||||
{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false},
|
||||
|
||||
{"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, false, true},
|
||||
{"HALT", 0x0021, 0xffff, DSPInterpreter::halt, NULL, 1, 0, {}, false, true},
|
||||
|
||||
{"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETO", 0x02de, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RET", 0x02df, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true},
|
||||
{"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RETO", 0x02de, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
{"RET", 0x02df, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true},
|
||||
|
||||
{"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, nop, 1, 0, {}, false, true},
|
||||
{"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, NULL, 1, 0, {}, false, true},
|
||||
|
||||
{"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLO", 0x02be, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALL", 0x02bf, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALLO", 0x02be, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"CALL", 0x02bf, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
|
||||
{"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true},
|
||||
{"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
{"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true},
|
||||
|
||||
{"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JL", 0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JG", 0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JC", 0x0297, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JO", 0x029e, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JL", 0x0291, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JG", 0x0292, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JC", 0x0297, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JO", 0x029e, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
|
||||
{"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
|
||||
{"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
{"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true},
|
||||
|
||||
{"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false},
|
||||
{"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false},
|
||||
{"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false},
|
||||
{"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false},
|
||||
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
{"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false},
|
||||
|
||||
{"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, false, false}, // discovered by ector!
|
||||
{"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, false, false}, // discovered by ector!
|
||||
{"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, NULL, 1, 0, {}, false, false}, // discovered by ector!
|
||||
{"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, NULL, 1, 0, {}, false, false}, // discovered by ector!
|
||||
|
||||
{"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, NULL, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
|
||||
{"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, NULL, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
|
||||
{"SI", 0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"SI", 0x1600, 0xff00, DSPInterpreter::si, NULL, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
|
||||
{"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
|
||||
{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, // F|RES: missing S64
|
||||
{"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, // F|RES: missing S64
|
||||
{"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
|
||||
{"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
{"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false},
|
||||
|
||||
{"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, // Hermes doesn't list this
|
||||
{"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, // Hermes doesn't list this
|
||||
{"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
|
||||
// LOOPS
|
||||
{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true},
|
||||
{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true},
|
||||
{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true},
|
||||
{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
{"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true},
|
||||
{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true},
|
||||
|
||||
// load and store value pointed by indexing reg and increment; LRR/SRR variants
|
||||
{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false},
|
||||
|
||||
{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false},
|
||||
|
||||
//2
|
||||
{"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"SRS", 0x2800, 0xf800, DSPInterpreter::srs, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false},
|
||||
{"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"SRS", 0x2800, 0xf800, DSPInterpreter::srs, NULL, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false},
|
||||
|
||||
// opcodes that can be extended
|
||||
// extended opcodes, note size of opcode will be set to 0
|
||||
|
||||
//3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
|
||||
{"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//4
|
||||
{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//5
|
||||
{"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//6
|
||||
{"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false},
|
||||
{"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//7
|
||||
{"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false},
|
||||
{"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"INC", 0x7600, 0xfe00, DSPInterpreter::inc, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//8
|
||||
{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 , 0, {}, true, false},
|
||||
{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 , 0, {}, true, false},
|
||||
{"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1 , 0, {}, true, false},
|
||||
{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 , 0, {}, true, false},
|
||||
{"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1 , 0, {}, true, false},
|
||||
{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 , 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false},
|
||||
{"NX", 0x8000, 0xf700, DSPInterpreter::nx, NULL, 1 , 0, {}, true, false},
|
||||
{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, NULL, 1 , 0, {}, true, false},
|
||||
{"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, NULL, 1 , 0, {}, true, false},
|
||||
{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, NULL, 1 , 0, {}, true, false},
|
||||
{"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, NULL, 1 , 0, {}, true, false},
|
||||
{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, NULL, 1 , 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
{"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
{"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
{"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
{"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, NULL, 1 , 0, {}, true, false},
|
||||
|
||||
//9
|
||||
{"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1 , 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MUL", 0x9000, 0xf700, DSPInterpreter::mul, NULL, 1 , 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//a-b
|
||||
{"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1 , 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false},
|
||||
{"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, NULL, 1 , 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false},
|
||||
{"ABS", 0xa100, 0xf700, DSPInterpreter::abs, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"TST", 0xb100, 0xf700, DSPInterpreter::tst, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false},
|
||||
|
||||
//c-d
|
||||
{"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1 , 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1 , 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, NULL, 1 , 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, NULL, 1 , 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false},
|
||||
{"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
|
||||
//e
|
||||
{"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, NULL, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, NULL, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, NULL, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false},
|
||||
{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, NULL, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false},
|
||||
|
||||
//f
|
||||
{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1 , 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false}, //Think the args are wrong
|
||||
{"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1 , 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false}, // clear acl0
|
||||
{"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, NULL, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , NULL, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false},
|
||||
{"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, NULL, 1 , 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false}, //Think the args are wrong
|
||||
{"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, NULL, 1 , 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false}, // clear acl0
|
||||
{"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false},
|
||||
};
|
||||
|
||||
const DSPOPCTemplate cw =
|
||||
{"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false};
|
||||
{"CW", 0x0000, 0x0000, NULL, NULL, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false};
|
||||
|
||||
|
||||
const DSPOPCTemplate opcodes_ext[] =
|
||||
{
|
||||
{"XXX", 0x0000, 0x00fc, DSPInterpreter::Ext::nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false},
|
||||
{"XXX", 0x0000, 0x00fc, DSPInterpreter::Ext::nop, &DSPEmitter::nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false},
|
||||
|
||||
{"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, &DSPEmitter::dr, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, &DSPEmitter::ir, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, NULL /*&DSPEmitter::nr*/, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, NULL /*&DSPEmitter::mv*/, 1, +2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false},
|
||||
|
||||
{"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false},
|
||||
{"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false},
|
||||
{"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, NULL /*&DSPEmitter::s*/, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false},
|
||||
{"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, NULL /*&DSPEmitter::sn*/, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false},
|
||||
|
||||
{"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, NULL /*&DSPEmitter::l*/, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, NULL /*&DSPEmitter::ln*/, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
|
||||
{"LS", 0x0080, 0x00ce, DSPInterpreter::Ext::ls, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SL", 0x0082, 0x00ce, DSPInterpreter::Ext::sl, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSN", 0x0084, 0x00ce, DSPInterpreter::Ext::lsn, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLN", 0x0086, 0x00ce, DSPInterpreter::Ext::sln, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSM", 0x0088, 0x00ce, DSPInterpreter::Ext::lsm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLM", 0x008a, 0x00ce, DSPInterpreter::Ext::slm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSNM", 0x008c, 0x00ce, DSPInterpreter::Ext::lsnm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLNM", 0x008e, 0x00ce, DSPInterpreter::Ext::slnm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LS", 0x0080, 0x00ce, DSPInterpreter::Ext::ls, NULL /*&DSPEmitter::ls*/, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SL", 0x0082, 0x00ce, DSPInterpreter::Ext::sl, NULL /*&DSPEmitter::sl*/, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSN", 0x0084, 0x00ce, DSPInterpreter::Ext::lsn, NULL /*&DSPEmitter::lsn*/, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLN", 0x0086, 0x00ce, DSPInterpreter::Ext::sln, NULL /*&DSPEmitter::sln*/, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSM", 0x0088, 0x00ce, DSPInterpreter::Ext::lsm, NULL /*&DSPEmitter::lsm*/, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLM", 0x008a, 0x00ce, DSPInterpreter::Ext::slm, NULL /*&DSPEmitter::slm*/, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
{"LSNM", 0x008c, 0x00ce, DSPInterpreter::Ext::lsnm, NULL /*&DSPEmitter::lsnm*/, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false},
|
||||
{"SLNM", 0x008e, 0x00ce, DSPInterpreter::Ext::slnm, NULL /*&DSPEmitter::slnm*/, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false},
|
||||
|
||||
{"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, NULL /*&DSPEmitter::ld*/, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, NULL /*&DSPEmitter::ldn*/, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, NULL /*&DSPEmitter::ldm*/, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
{"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, NULL /*&DSPEmitter::ldnm*/, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false},
|
||||
};
|
||||
|
||||
const int opcodes_size = sizeof(opcodes) / sizeof(DSPOPCTemplate);
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@
|
|||
#ifndef _DSPTABLES_H
|
||||
#define _DSPTABLES_H
|
||||
|
||||
#include "Common.h"
|
||||
//nclude "Common.h"
|
||||
#include "DSPEmitter.h"
|
||||
#include "DSPCommon.h"
|
||||
|
||||
// The non-ADDR ones that end with _D are the opposite one - if the bit specify
|
||||
// ACC0, then ACC_D will be ACC1.
|
||||
|
|
@ -67,9 +69,8 @@ enum partype_t
|
|||
#define OPTABLE_SIZE 0xffff + 1
|
||||
#define EXT_OPTABLE_SIZE 0xff + 1
|
||||
|
||||
typedef u16 UDSPInstruction;
|
||||
|
||||
typedef void (*dspInstFunc)(const UDSPInstruction);
|
||||
typedef void (*dspIntFunc)(const UDSPInstruction);
|
||||
typedef void (DSPEmitter::*dspJitFunc)(const UDSPInstruction);
|
||||
|
||||
struct param2_t
|
||||
{
|
||||
|
|
@ -86,8 +87,8 @@ typedef struct
|
|||
u16 opcode;
|
||||
u16 opcode_mask;
|
||||
|
||||
dspInstFunc interpFunc;
|
||||
dspInstFunc jitFunc;
|
||||
dspIntFunc intFunc;
|
||||
dspJitFunc jitFunc;
|
||||
|
||||
u8 size;
|
||||
u8 param_count;
|
||||
|
|
@ -141,11 +142,11 @@ inline void ExecuteInstruction(const UDSPInstruction inst)
|
|||
|
||||
if (tinst->extended) {
|
||||
if ((inst >> 12) == 0x3)
|
||||
extOpTable[inst & 0x7F]->interpFunc(inst);
|
||||
extOpTable[inst & 0x7F]->intFunc(inst);
|
||||
else
|
||||
extOpTable[inst & 0xFF]->interpFunc(inst);
|
||||
extOpTable[inst & 0xFF]->intFunc(inst);
|
||||
}
|
||||
tinst->interpFunc(inst);
|
||||
tinst->intFunc(inst);
|
||||
if (tinst->extended) {
|
||||
applyWriteBackLog();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,425 @@
|
|||
// Copyright (C) 2003 Dolphin Project.
|
||||
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, version 2.0.
|
||||
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License 2.0 for more details.
|
||||
|
||||
// A copy of the GPL 2.0 should have been included with the program.
|
||||
// If not, see http://www.gnu.org/licenses/
|
||||
|
||||
// Official SVN repository and contact information can be found at
|
||||
// http://code.google.com/p/dolphin-emu/
|
||||
#include "../DSPMemoryMap.h"
|
||||
#include "../DSPEmitter.h"
|
||||
#include "../DSPIntExtOps.h" // remove when getting rid of writebacklog
|
||||
// See docs in the interpeter
|
||||
|
||||
inline bool IsSameMemArea(u16 a, u16 b)
|
||||
{
|
||||
//LM: tested on WII
|
||||
if ((a>>10)==(b>>10))
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
// DR $arR
|
||||
// xxxx xxxx 0000 01rr
|
||||
// Decrement addressing register $arR.
|
||||
void DSPEmitter::dr(const UDSPInstruction opc) {
|
||||
decrement_addr_reg(opc & 0x3);
|
||||
}
|
||||
|
||||
// IR $arR
|
||||
// xxxx xxxx 0000 10rr
|
||||
// Increment addressing register $arR.
|
||||
void DSPEmitter::ir(const UDSPInstruction opc) {
|
||||
increment_addr_reg(opc & 0x3);
|
||||
}
|
||||
|
||||
// NR $arR
|
||||
// xxxx xxxx 0000 11rr
|
||||
// Add corresponding indexing register $ixR to addressing register $arR.
|
||||
void DSPEmitter::nr(const UDSPInstruction opc) {
|
||||
u8 reg = opc & 0x3;
|
||||
|
||||
increase_addr_reg(reg);
|
||||
}
|
||||
|
||||
// MV $axD.D, $acS.S
|
||||
// xxxx xxxx 0001 ddss
|
||||
// Move value of $acS.S to the $axD.D.
|
||||
void DSPEmitter::mv(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x3) + DSP_REG_ACL0;
|
||||
u8 dreg = ((opc >> 2) & 0x3);
|
||||
|
||||
#if 0 //more tests
|
||||
if ((sreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
|
||||
writeToBackLog(0, dreg + DSP_REG_AXL0, ((u16)dsp_get_acc_h(sreg-DSP_REG_ACM0) & 0x0080) ? 0x8000 : 0x7fff);
|
||||
else
|
||||
#endif
|
||||
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
|
||||
}
|
||||
|
||||
// S @$arD, $acS.S
|
||||
// xxxx xxxx 001s s0dd
|
||||
// Store value of $acS.S in the memory pointed by register $arD.
|
||||
// Post increment register $arD.
|
||||
void DSPEmitter::s(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = opc & 0x3;
|
||||
u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
|
||||
|
||||
ext_dmem_write(dreg, sreg);
|
||||
increment_addr_reg(dreg);
|
||||
}
|
||||
|
||||
// SN @$arD, $acS.S
|
||||
// xxxx xxxx 001s s1dd
|
||||
// Store value of register $acS.S in the memory pointed by register $arD.
|
||||
// Add indexing register $ixD to register $arD.
|
||||
void DSPEmitter::sn(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = opc & 0x3;
|
||||
u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
|
||||
|
||||
ext_dmem_write(dreg, sreg);
|
||||
increase_addr_reg(dreg);
|
||||
}
|
||||
|
||||
// L $axD.D, @$arS
|
||||
// xxxx xxxx 01dd d0ss
|
||||
// Load $axD.D/$acD.D with value from memory pointed by register $arS.
|
||||
// Post increment register $arS.
|
||||
void DSPEmitter::l(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = opc & 0x3;
|
||||
u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
|
||||
|
||||
if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
|
||||
{
|
||||
u16 val = ext_dmem_read(g_dsp.r[sreg]);
|
||||
writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
|
||||
writeToBackLog(1, dreg, val);
|
||||
writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
|
||||
increment_addr_reg(sreg);
|
||||
}
|
||||
else
|
||||
{
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[sreg]));
|
||||
increment_addr_reg(sreg);
|
||||
}
|
||||
}
|
||||
|
||||
// LN $axD.D, @$arS
|
||||
// xxxx xxxx 01dd d0ss
|
||||
// Load $axD.D/$acD.D with value from memory pointed by register $arS.
|
||||
// Add indexing register register $ixS to register $arS.
|
||||
void DSPEmitter::ln(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = opc & 0x3;
|
||||
u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
|
||||
|
||||
if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
|
||||
{
|
||||
u16 val = ext_dmem_read(g_dsp.r[sreg]);
|
||||
writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
|
||||
writeToBackLog(1, dreg, val);
|
||||
writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
|
||||
increase_addr_reg(sreg);
|
||||
}
|
||||
else
|
||||
{
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[sreg]));
|
||||
increase_addr_reg(sreg);
|
||||
}
|
||||
}
|
||||
|
||||
// LS $axD.D, $acS.m
|
||||
// xxxx xxxx 10dd 000s
|
||||
// Load register $axD.D with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Increment both $ar0 and $ar3.
|
||||
void DSPEmitter::ls(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR3, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR0]));
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
increment_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
|
||||
// LSN $axD.D, $acS.m
|
||||
// xxxx xxxx 10dd 010s
|
||||
// Load register $axD.D with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix0 to addressing
|
||||
// register $ar0 and increment $ar3.
|
||||
void DSPEmitter::lsn(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR3, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR0]));
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
increase_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// LSM $axD.D, $acS.m
|
||||
// xxxx xxxx 10dd 100s
|
||||
// Load register $axD.D with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix3 to addressing
|
||||
// register $ar3 and increment $ar0.
|
||||
void DSPEmitter::lsm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR3, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR0]));
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
increment_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// LSMN $axD.D, $acS.m
|
||||
// xxxx xxxx 10dd 110s
|
||||
// Load register $axD.D with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix0 to addressing
|
||||
// register $ar0 and add corresponding indexing register $ix3 to addressing
|
||||
// register $ar3.
|
||||
void DSPEmitter::lsnm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR3, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR0]));
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
increase_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// SL $acS.m, $axD.D
|
||||
// xxxx xxxx 10dd 001s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $axD.D with value from memory pointed by register
|
||||
// $ar3. Increment both $ar0 and $ar3.
|
||||
void DSPEmitter::sl(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR0, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
increment_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// SLN $acS.m, $axD.D
|
||||
// xxxx xxxx 10dd 011s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $axD.D with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
|
||||
// and increment $ar3.
|
||||
void DSPEmitter::sln(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR0, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
increase_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// SLM $acS.m, $axD.D
|
||||
// xxxx xxxx 10dd 101s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $axD.D with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix3 to addressing register $ar3
|
||||
// and increment $ar0.
|
||||
void DSPEmitter::slm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR0, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
increment_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// SLMN $acS.m, $axD.D
|
||||
// xxxx xxxx 10dd 111s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $axD.D with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
|
||||
// and add corresponding indexing register $ix3 to addressing register $ar3.
|
||||
void DSPEmitter::slnm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
|
||||
u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
|
||||
ext_dmem_write(DSP_REG_AR0, sreg);
|
||||
|
||||
writeToBackLog(0, dreg, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
increase_addr_reg(DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// LD $ax0.d, $ax1.r, @$arS
|
||||
// xxxx xxxx 11dr 00ss
|
||||
// example for "nx'ld $AX0.L, $AX1.L, @$AR3"
|
||||
// Loads the word pointed by AR0 to AX0.H, then loads the word pointed by AR3
|
||||
// to AX0.L. Increments AR0 and AR3. If AR0 and AR3 point into the same
|
||||
// memory page (upper 6 bits of addr are the same -> games are not doing that!)
|
||||
// then the value pointed by AR0 is loaded to BOTH AX0.H and AX0.L. If AR0
|
||||
// points into an invalid memory page (ie 0x2000), then AX0.H keeps its old
|
||||
// value. (not implemented yet) If AR3 points into an invalid memory page, then
|
||||
// AX0.L gets the same value as AX0.H. (not implemented yet)
|
||||
void DSPEmitter::ld(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x1;
|
||||
u8 rreg = (opc >> 4) & 0x1;
|
||||
u8 sreg = opc & 0x3;
|
||||
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increment_addr_reg(sreg);
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXH0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increment_addr_reg(dreg);
|
||||
}
|
||||
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDN $ax0.d, $ax1.r, @$arS
|
||||
// xxxx xxxx 11dr 01ss
|
||||
void DSPEmitter::ldn(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x1;
|
||||
u8 rreg = (opc >> 4) & 0x1;
|
||||
u8 sreg = opc & 0x3;
|
||||
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increase_addr_reg(sreg);
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXH0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increase_addr_reg(dreg);
|
||||
}
|
||||
|
||||
increment_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDM $ax0.d, $ax1.r, @$arS
|
||||
// xxxx xxxx 11dr 10ss
|
||||
void DSPEmitter::ldm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x1;
|
||||
u8 rreg = (opc >> 4) & 0x1;
|
||||
u8 sreg = opc & 0x3;
|
||||
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increment_addr_reg(sreg);
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXH0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increment_addr_reg(dreg);
|
||||
}
|
||||
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDNM $ax0.d, $ax1.r, @$arS
|
||||
// xxxx xxxx 11dr 11ss
|
||||
void DSPEmitter::ldnm(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x1;
|
||||
u8 rreg = (opc >> 4) & 0x1;
|
||||
u8 sreg = opc & 0x3;
|
||||
|
||||
if (sreg != DSP_REG_AR3) {
|
||||
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[sreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[sreg]));
|
||||
else
|
||||
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increase_addr_reg(sreg);
|
||||
} else {
|
||||
writeToBackLog(0, rreg + DSP_REG_AXH0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
|
||||
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[dreg]));
|
||||
else
|
||||
writeToBackLog(1, rreg + DSP_REG_AXL0, ext_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
||||
|
||||
increase_addr_reg(dreg);
|
||||
}
|
||||
|
||||
increase_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
|
||||
void DSPEmitter::writeAxAcc(const UDSPInstruction opc) {
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
// Copyright (C) 2010 Dolphin Project.
|
||||
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, version 2.0.
|
||||
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License 2.0 for more details.
|
||||
|
||||
// A copy of the GPL 2.0 should have been included with the program.
|
||||
// If not, see http://www.gnu.org/licenses/
|
||||
|
||||
// Official SVN repository and contact information can be found at
|
||||
// http://code.google.com/p/dolphin-emu/
|
||||
|
||||
#ifndef _DSP_JIT_UTIL_H
|
||||
#define _DSP_JIT_UTIL_H
|
||||
|
||||
#include "../DSPMemoryMap.h"
|
||||
#include "../DSPEmitter.h"
|
||||
#include "x64Emitter.h"
|
||||
#include "ABI.h"
|
||||
|
||||
using namespace Gen;
|
||||
|
||||
// HORRIBLE UGLINESS, someone please fix.
|
||||
// See http://code.google.com/p/dolphin-emu/source/detail?r=3125
|
||||
void DSPEmitter::increment_addr_reg(int reg)
|
||||
{
|
||||
ABI_PushAllCalleeSavedRegsAndAdjustStack();
|
||||
|
||||
// u16 tmb = g_dsp.r[DSP_REG_WR0 + reg];
|
||||
MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_WR0 + reg]));
|
||||
|
||||
// tmb = tmb | (tmb >> 8);
|
||||
MOV(16, R(EBX), R(EAX));
|
||||
SHR(16, R(EBX), Imm8(8));
|
||||
OR(16, R(EAX), R(EBX));
|
||||
|
||||
// tmb = tmb | (tmb >> 4);
|
||||
MOV(16, R(EBX), R(EAX));
|
||||
SHR(16, R(EBX), Imm8(4));
|
||||
OR(16, R(EAX), R(EBX));
|
||||
|
||||
// tmb = tmb | (tmb >> 2);
|
||||
MOV(16, R(EBX), R(EAX));
|
||||
SHR(16, R(EBX), Imm8(2));
|
||||
OR(16, R(EAX), R(EBX));
|
||||
|
||||
// tmb = tmb | (tmb >> 1);
|
||||
MOV(16, R(EBX), R(EAX));
|
||||
SHR(16, R(EBX), Imm8(1));
|
||||
OR(16, R(EAX), R(EBX));
|
||||
|
||||
// s16 tmp = g_dsp.r[reg];
|
||||
MOV(16, R(EBX), M(&g_dsp.r[reg]));
|
||||
|
||||
// if ((tmp & tmb) == tmb)
|
||||
AND(16, R(EAX), R(EBX));
|
||||
CMP(16, R(EAX), R(EBX));
|
||||
FixupBranch not_equal = J_CC(CC_NZ);
|
||||
|
||||
// tmp ^= g_dsp.r[DSP_REG_WR0 + reg];
|
||||
XOR(16, R(EBX), M(&g_dsp.r[DSP_REG_WR0 + reg]));
|
||||
|
||||
FixupBranch end = J();
|
||||
SetJumpTarget(not_equal);
|
||||
// tmp++;
|
||||
ADD(16, R(EBX), Imm8(1));
|
||||
|
||||
SetJumpTarget(end);
|
||||
|
||||
// g_dsp.r[reg] = tmp;
|
||||
MOV(16, M(&g_dsp.r[reg]), R(EBX));
|
||||
|
||||
ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
||||
|
||||
}
|
||||
|
||||
// See http://code.google.com/p/dolphin-emu/source/detail?r=3125
|
||||
void DSPEmitter::decrement_addr_reg(int reg)
|
||||
{
|
||||
ABI_PushAllCalleeSavedRegsAndAdjustStack();
|
||||
|
||||
// s16 tmp = g_dsp.r[reg];
|
||||
MOV(16, R(EAX), M(&g_dsp.r[reg]));
|
||||
|
||||
// if ((tmp & g_dsp.r[DSP_REG_WR0 + reg]) == 0)
|
||||
MOV(16, R(EBX), R(EAX));
|
||||
AND(16, R(EBX), M(&g_dsp.r[DSP_REG_WR0 + reg]));
|
||||
CMP(16, R(EBX), Imm8(0));
|
||||
FixupBranch not_equal = J_CC(CC_NZ);
|
||||
|
||||
// tmp |= g_dsp.r[DSP_REG_WR0 + reg];
|
||||
OR(16, R(EAX), M(&g_dsp.r[DSP_REG_WR0 + reg]));
|
||||
|
||||
FixupBranch end = J();
|
||||
SetJumpTarget(not_equal);
|
||||
// tmp--;
|
||||
SUB(16, R(EAX), Imm8(1));
|
||||
|
||||
SetJumpTarget(end);
|
||||
|
||||
// g_dsp.r[reg] = tmp;
|
||||
MOV(16, M(&g_dsp.r[reg]), R(EAX));
|
||||
|
||||
ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
||||
}
|
||||
|
||||
// Increase addr register according to the correspond ix register
|
||||
void DSPEmitter::increase_addr_reg(int reg)
|
||||
{
|
||||
|
||||
/*
|
||||
MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_IX0 + reg]));
|
||||
|
||||
CMP(16, R(EAX), Imm16(0));
|
||||
FixupBranch end = J_CC(CC_Z);
|
||||
FixupBranch negValue = J_CC(CC_L);
|
||||
|
||||
ABI_CallFunctionC((void *)increment_addr_reg, reg);
|
||||
|
||||
FixupBranch posValue = J();
|
||||
|
||||
SetJumpTarget(negValue);
|
||||
ABI_CallFunctionC((void *)decrement_addr_reg, reg);
|
||||
|
||||
SetJumpTarget(posValue);
|
||||
SetJumpTarget(end);
|
||||
*/
|
||||
|
||||
// TODO: DO RIGHT!
|
||||
s16 value = (s16)g_dsp.r[DSP_REG_IX0 + reg];
|
||||
|
||||
if (value > 0) {
|
||||
for (int i = 0; i < value; i++) {
|
||||
increment_addr_reg(reg);
|
||||
}
|
||||
} else if (value < 0) {
|
||||
for (int i = 0; i < (int)(-value); i++) {
|
||||
decrement_addr_reg(reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Decrease addr register according to the correspond ix register
|
||||
void DSPEmitter::decrease_addr_reg(int reg)
|
||||
{
|
||||
// TODO: DO RIGHT!
|
||||
|
||||
s16 value = (s16)g_dsp.r[DSP_REG_IX0 + reg];
|
||||
|
||||
if (value > 0) {
|
||||
for (int i = 0; i < value; i++) {
|
||||
decrement_addr_reg(reg);
|
||||
}
|
||||
} else if (value < 0) {
|
||||
for (int i = 0; i < (int)(-value); i++) {
|
||||
increment_addr_reg(reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void DSPEmitter::ext_dmem_write(u32 dest, u32 src)
|
||||
{
|
||||
|
||||
u16 addr = g_dsp.r[dest];
|
||||
u16 val = g_dsp.r[src];
|
||||
switch (addr >> 12) {
|
||||
case 0x0: // 0xxx DRAM
|
||||
g_dsp.dram[addr & DSP_DRAM_MASK] = val;
|
||||
break;
|
||||
|
||||
case 0x1: // 1xxx COEF
|
||||
ERROR_LOG(DSPLLE, "Illegal write to COEF (pc = %02x)", g_dsp.pc);
|
||||
break;
|
||||
|
||||
case 0xf: // Fxxx HW regs
|
||||
// Can ext write to ifx?
|
||||
// gdsp_ifx_write(addr, val);
|
||||
ERROR_LOG(DSPLLE, "Illegal write to ifx (pc = %02x)", g_dsp.pc);
|
||||
break;
|
||||
|
||||
default: // Unmapped/non-existing memory
|
||||
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory", g_dsp.pc, addr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
u16 DSPEmitter::ext_dmem_read(u16 addr)
|
||||
{
|
||||
switch (addr >> 12) {
|
||||
case 0x0: // 0xxx DRAM
|
||||
return g_dsp.dram[addr & DSP_DRAM_MASK];
|
||||
|
||||
case 0x1: // 1xxx COEF
|
||||
NOTICE_LOG(DSPLLE, "%04x : Coef Read @ %04x", g_dsp.pc, addr);
|
||||
return g_dsp.coef[addr & DSP_COEF_MASK];
|
||||
|
||||
case 0xf: // Fxxx HW regs
|
||||
// Can ext read from ifx?
|
||||
ERROR_LOG(DSPLLE, "Illegal read from ifx (pc = %02x)", g_dsp.pc);
|
||||
// return gdsp_ifx_read(addr);
|
||||
|
||||
default: // Unmapped/non-existing memory
|
||||
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory", g_dsp.pc, addr);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -18,12 +18,15 @@ files = [
|
|||
"DspIntLoadStore.cpp",
|
||||
"DspIntMisc.cpp",
|
||||
"DspIntMultiplier.cpp",
|
||||
"DSPJit.cpp",
|
||||
"DSPEmitter.cpp",
|
||||
"DSPCodeUtil.cpp",
|
||||
"LabelMap.cpp",
|
||||
"DSPInterpreter.cpp",
|
||||
"DSPCore.cpp",
|
||||
"DSPTables.cpp",
|
||||
"Jit/DSPJitExtOps.cpp",
|
||||
"Jit/DSPJitUtil.cpp",
|
||||
|
||||
]
|
||||
|
||||
acenv = env.Clone()
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ bool DSPDisassembler::DisOpcode(const u16 *binbuf, int base_addr, int pass, u16
|
|||
break;
|
||||
}
|
||||
}
|
||||
const DSPOPCTemplate fake_op = {"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false};
|
||||
const DSPOPCTemplate fake_op = {"CW", 0x0000, 0x0000, nop, NULL, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false};
|
||||
if (!opc)
|
||||
opc = &fake_op;
|
||||
|
||||
|
|
|
|||
|
|
@ -303,7 +303,8 @@ unsigned short DSP_ReadControlRegister()
|
|||
void DSP_Update(int cycles)
|
||||
{
|
||||
// This is called OFTEN - better not do anything expensive!
|
||||
CDSPHandler::GetInstance().Update(cycles);
|
||||
// ~1/6th as many cycles as the period PPC-side.
|
||||
CDSPHandler::GetInstance().Update(cycles / 6);
|
||||
}
|
||||
|
||||
// The reason that we don't disable this entire
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ BEGIN_EVENT_TABLE(DSPConfigDialogLLE, wxDialog)
|
|||
EVT_BUTTON(wxID_OK, DSPConfigDialogLLE::SettingsChanged)
|
||||
EVT_CHECKBOX(ID_ENABLE_DTK_MUSIC, DSPConfigDialogLLE::SettingsChanged)
|
||||
EVT_CHECKBOX(ID_ENABLE_THROTTLE, DSPConfigDialogLLE::SettingsChanged)
|
||||
EVT_CHECKBOX(ID_ENABLE_JIT, DSPConfigDialogLLE::SettingsChanged)
|
||||
EVT_CHOICE(ID_BACKEND, DSPConfigDialogLLE::BackendChanged)
|
||||
EVT_COMMAND_SCROLL(ID_VOLUME, DSPConfigDialogLLE::VolumeChanged)
|
||||
END_EVENT_TABLE()
|
||||
|
|
@ -41,6 +42,7 @@ DSPConfigDialogLLE::DSPConfigDialogLLE(wxWindow *parent, wxWindowID id, const wx
|
|||
// Create items
|
||||
m_buttonEnableDTKMusic = new wxCheckBox(this, ID_ENABLE_DTK_MUSIC, wxT("Enable DTK Music"), wxDefaultPosition, wxDefaultSize, 0, wxDefaultValidator);
|
||||
m_buttonEnableThrottle = new wxCheckBox(this, ID_ENABLE_THROTTLE, wxT("Enable Audio Throttle"), wxDefaultPosition, wxDefaultSize, 0, wxDefaultValidator);
|
||||
m_buttonEnableJIT = new wxCheckBox(this, ID_ENABLE_JIT, wxT("Enable JIT Dynarec"), wxDefaultPosition, wxDefaultSize, 0, wxDefaultValidator);
|
||||
wxStaticText *BackendText = new wxStaticText(this, wxID_ANY, wxT("Audio Backend"), wxDefaultPosition, wxDefaultSize, 0);
|
||||
m_BackendSelection = new wxChoice(this, ID_BACKEND, wxDefaultPosition, wxSize(90, 20), wxArrayBackends, 0, wxDefaultValidator, wxEmptyString);
|
||||
|
||||
|
|
@ -51,6 +53,7 @@ DSPConfigDialogLLE::DSPConfigDialogLLE(wxWindow *parent, wxWindowID id, const wx
|
|||
// Update values
|
||||
m_buttonEnableDTKMusic->SetValue(ac_Config.m_EnableDTKMusic ? true : false);
|
||||
m_buttonEnableThrottle->SetValue(ac_Config.m_EnableThrottle ? true : false);
|
||||
m_buttonEnableJIT->SetValue(ac_Config.m_EnableJIT ? true : false);
|
||||
|
||||
// Add tooltips
|
||||
m_buttonEnableDTKMusic->SetToolTip(wxT("This is used to play music tracks, like BGM."));
|
||||
|
|
@ -58,6 +61,8 @@ DSPConfigDialogLLE::DSPConfigDialogLLE(wxWindow *parent, wxWindowID id, const wx
|
|||
wxT("Disabling this could cause abnormal game speed, such as too fast.\n")
|
||||
wxT("But sometimes enabling this could cause constant noise.\n")
|
||||
wxT("\nKeyboard Shortcut <TAB>: Hold down to instantly disable Throttle."));
|
||||
m_buttonEnableJIT->SetToolTip(wxT("Enables dynamic recompilation of DSP code.\n")
|
||||
wxT("Changing this will have no effect while the emulator is running!"));
|
||||
m_BackendSelection->SetToolTip(wxT("Changing this will have no effect while the emulator is running!"));
|
||||
m_volumeSlider->SetToolTip(wxT("This setting only affects DSound and OpenAL."));
|
||||
|
||||
|
|
@ -69,6 +74,7 @@ DSPConfigDialogLLE::DSPConfigDialogLLE(wxWindow *parent, wxWindowID id, const wx
|
|||
|
||||
sbSettings->Add(m_buttonEnableDTKMusic, 0, wxALL, 5);
|
||||
sbSettings->Add(m_buttonEnableThrottle, 0, wxALL, 5);
|
||||
sbSettings->Add(m_buttonEnableJIT, 0, wxALL, 5);
|
||||
|
||||
sBackend->Add(BackendText, 0, wxALIGN_CENTER|wxALL, 5);
|
||||
sBackend->Add(m_BackendSelection, 0, wxALL, 1);
|
||||
|
|
@ -125,6 +131,7 @@ void DSPConfigDialogLLE::SettingsChanged(wxCommandEvent& event)
|
|||
{
|
||||
ac_Config.m_EnableDTKMusic = m_buttonEnableDTKMusic->GetValue();
|
||||
ac_Config.m_EnableThrottle = m_buttonEnableThrottle->GetValue();
|
||||
ac_Config.m_EnableJIT = m_buttonEnableJIT->GetValue();
|
||||
|
||||
#ifdef __APPLE__
|
||||
strncpy(ac_Config.sBackend, m_BackendSelection->GetStringSelection().mb_str(), 128);
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ private:
|
|||
wxButton *m_OK;
|
||||
wxCheckBox *m_buttonEnableDTKMusic;
|
||||
wxCheckBox *m_buttonEnableThrottle;
|
||||
wxCheckBox *m_buttonEnableJIT;
|
||||
wxArrayString wxArrayBackends;
|
||||
wxChoice *m_BackendSelection;
|
||||
|
||||
|
|
@ -52,6 +53,7 @@ private:
|
|||
{
|
||||
ID_ENABLE_DTK_MUSIC,
|
||||
ID_ENABLE_THROTTLE,
|
||||
ID_ENABLE_JIT,
|
||||
ID_BACKEND,
|
||||
ID_VOLUME
|
||||
};
|
||||
|
|
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|||
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@ -49,6 +49,7 @@ SoundStream *soundStream = NULL;
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bool g_InitMixer = false;
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bool bIsRunning = false;
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u32 cycle_count = 0;
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// Standard crap to make wxWidgets happy
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#ifdef _WIN32
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@ -218,7 +219,17 @@ THREAD_RETURN dsp_thread(void* lpParameter)
|
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{
|
||||
while (bIsRunning)
|
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{
|
||||
DSPInterpreter::Run();
|
||||
u32 cycles = 0;
|
||||
|
||||
if (jit)
|
||||
{
|
||||
cycles = cycle_count;
|
||||
DSPCore_RunCycles(cycles);
|
||||
}
|
||||
else
|
||||
DSPInterpreter::Run();
|
||||
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||||
cycle_count -= cycles;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -241,7 +252,7 @@ void Initialize(void *init)
|
|||
|
||||
std::string irom_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_IROM;
|
||||
std::string coef_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_COEF;
|
||||
bCanWork = DSPCore_Init(irom_filename.c_str(), coef_filename.c_str());
|
||||
bCanWork = DSPCore_Init(irom_filename.c_str(), coef_filename.c_str(), AudioCommon::UseJIT());
|
||||
|
||||
g_dsp.cpu_ram = g_dspInitialize.pGetMemoryPointer(0);
|
||||
DSPCore_Reset();
|
||||
|
|
@ -363,6 +374,7 @@ void DSP_WriteMailboxLow(bool _CPUMailbox, u16 _uLowMail)
|
|||
|
||||
void DSP_Update(int cycles)
|
||||
{
|
||||
int cyclesRatio = cycles / (jit?20:6);
|
||||
// Sound stream update job has been handled by AudioDMA routine, which is more efficient
|
||||
/*
|
||||
// This gets called VERY OFTEN. The soundstream update might be expensive so only do it 200 times per second or something.
|
||||
|
|
@ -385,7 +397,12 @@ void DSP_Update(int cycles)
|
|||
// If we're not on a thread, run cycles here.
|
||||
if (!g_dspInitialize.bOnThread)
|
||||
{
|
||||
DSPCore_RunCycles(cycles);
|
||||
// ~1/6th as many cycles as the period PPC-side.
|
||||
DSPCore_RunCycles(cyclesRatio);;
|
||||
}
|
||||
else
|
||||
{
|
||||
cycle_count += (cyclesRatio);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue