[AArch64] Implement a bunch of integer instructions
16 new instructions for AArch64.
This commit is contained in:
Ryan Houdek
parent
5671530026
commit
47e47891d4
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@ -225,6 +225,7 @@ elseif(_M_ARM_64)
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PowerPC/JitArm64/JitArm64Cache.cpp
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PowerPC/JitArm64/JitArm64_RegCache.cpp
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PowerPC/JitArm64/JitArm64_Branch.cpp
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PowerPC/JitArm64/JitArm64_Integer.cpp
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PowerPC/JitArm64/JitArm64_LoadStore.cpp
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PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
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PowerPC/JitArm64/JitArm64_Tables.cpp)
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@ -77,6 +77,10 @@ public:
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void bcctrx(UGeckoInstruction inst);
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void bclrx(UGeckoInstruction inst);
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// Integer
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void arith_imm(UGeckoInstruction inst);
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void boolX(UGeckoInstruction inst);
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// System Registers
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void mtmsr(UGeckoInstruction inst);
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@ -102,5 +106,10 @@ private:
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void WriteExitDestInR(ARM64Reg dest);
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FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set);
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void ComputeRC(u32 d);
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typedef u32 (*Operation)(u32, u32);
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void reg_imm(u32 d, u32 a, bool binary, u32 value, Operation do_op, void (ARM64XEmitter::*op)(ARM64Reg, ARM64Reg, ARM64Reg, ArithOption), bool Rc = false);
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};
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@ -0,0 +1,229 @@
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// Copyright 2014 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "Common/Arm64Emitter.h"
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#include "Common/Common.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/JitArm64/Jit.h"
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#include "Core/PowerPC/JitArm64/JitArm64_RegCache.h"
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#include "Core/PowerPC/JitArm64/JitAsm.h"
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using namespace Arm64Gen;
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void JitArm64::ComputeRC(u32 d)
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{
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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if (gpr.IsImm(d))
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{
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MOVI2R(XA, gpr.GetImm(d));
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SXTW(XA, XA);
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}
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else
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{
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SXTW(XA, gpr.R(d));
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}
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STR(INDEX_UNSIGNED, XA, X29, PPCSTATE_OFF(cr_val[0]));
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gpr.Unlock(WA);
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}
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// Following static functions are used in conjunction with reg_imm
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static u32 Add(u32 a, u32 b)
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{
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return a + b;
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}
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static u32 Or(u32 a, u32 b)
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{
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return a | b;
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}
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static u32 And(u32 a, u32 b)
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{
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return a & b;
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}
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static u32 Xor(u32 a, u32 b)
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{
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return a ^ b;
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}
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void JitArm64::reg_imm(u32 d, u32 a, bool binary, u32 value, Operation do_op, void (ARM64XEmitter::*op)(ARM64Reg, ARM64Reg, ARM64Reg, ArithOption), bool Rc)
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{
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if (a || binary)
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{
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if (gpr.IsImm(a))
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{
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gpr.SetImmediate(d, do_op(gpr.GetImm(a), value));
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}
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else
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{
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ARM64Reg WA = gpr.GetReg();
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MOVI2R(WA, value);
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(this->*op)(gpr.R(d), gpr.R(a), WA, ArithOption(WA, ST_LSL, 0));
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gpr.Unlock(WA);
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}
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if (Rc)
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ComputeRC(d);
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}
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else if (do_op == Add)
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{
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// a == 0, implies zero register
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gpr.SetImmediate(d, value);
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if (Rc)
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ComputeRC(d);
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}
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else
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{
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_assert_msg_(DYNA_REC, false, "Hit impossible condition in reg_imm!");
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}
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}
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void JitArm64::arith_imm(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITIntegerOff);
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u32 d = inst.RD, a = inst.RA, s = inst.RS;
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switch (inst.OPCD)
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{
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case 14: // addi
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reg_imm(d, a, false, (u32)(s32)inst.SIMM_16, Add, &ARM64XEmitter::ADD);
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break;
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case 15: // addis
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reg_imm(d, a, false, (u32)inst.SIMM_16 << 16, Add, &ARM64XEmitter::ADD);
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break;
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case 24: // ori
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if (a == 0 && s == 0 && inst.UIMM == 0 && !inst.Rc) //check for nop
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{
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// NOP
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return;
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}
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reg_imm(a, s, true, inst.UIMM, Or, &ARM64XEmitter::ORR);
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break;
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case 25: // oris
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reg_imm(a, s, true, inst.UIMM << 16, Or, &ARM64XEmitter::ORR);
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break;
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case 28: // andi
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reg_imm(a, s, true, inst.UIMM, And, &ARM64XEmitter::AND, true);
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break;
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case 29: // andis
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reg_imm(a, s, true, inst.UIMM << 16, And, &ARM64XEmitter::AND, true);
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break;
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case 26: // xori
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reg_imm(a, s, true, inst.UIMM, Xor, &ARM64XEmitter::EOR);
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break;
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case 27: // xoris
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reg_imm(a, s, true, inst.UIMM << 16, Xor, &ARM64XEmitter::EOR);
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break;
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}
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}
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void JitArm64::boolX(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITIntegerOff);
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int a = inst.RA, s = inst.RS, b = inst.RB;
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if (gpr.IsImm(s) && gpr.IsImm(b))
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{
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if (inst.SUBOP10 == 28) // andx
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gpr.SetImmediate(a, (u32)gpr.GetImm(s) & (u32)gpr.GetImm(b));
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else if (inst.SUBOP10 == 476) // nandx
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gpr.SetImmediate(a, ~((u32)gpr.GetImm(s) & (u32)gpr.GetImm(b)));
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else if (inst.SUBOP10 == 60) // andcx
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gpr.SetImmediate(a, (u32)gpr.GetImm(s) & (~(u32)gpr.GetImm(b)));
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else if (inst.SUBOP10 == 444) // orx
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gpr.SetImmediate(a, (u32)gpr.GetImm(s) | (u32)gpr.GetImm(b));
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else if (inst.SUBOP10 == 124) // norx
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gpr.SetImmediate(a, ~((u32)gpr.GetImm(s) | (u32)gpr.GetImm(b)));
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else if (inst.SUBOP10 == 412) // orcx
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gpr.SetImmediate(a, (u32)gpr.GetImm(s) | (~(u32)gpr.GetImm(b)));
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else if (inst.SUBOP10 == 316) // xorx
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gpr.SetImmediate(a, (u32)gpr.GetImm(s) ^ (u32)gpr.GetImm(b));
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else if (inst.SUBOP10 == 284) // eqvx
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gpr.SetImmediate(a, ~((u32)gpr.GetImm(s) ^ (u32)gpr.GetImm(b)));
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if (inst.Rc)
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ComputeRC(a);
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}
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else if (s == b)
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{
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if ((inst.SUBOP10 == 28 /* andx */) || (inst.SUBOP10 == 444 /* orx */))
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{
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if (a != s)
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{
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MOV(gpr.R(a), gpr.R(s));
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}
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}
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else if ((inst.SUBOP10 == 476 /* nandx */) || (inst.SUBOP10 == 124 /* norx */))
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{
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MVN(gpr.R(a), gpr.R(s));
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}
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else if ((inst.SUBOP10 == 412 /* orcx */) || (inst.SUBOP10 == 284 /* eqvx */))
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{
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gpr.SetImmediate(a, 0xFFFFFFFF);
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}
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else if ((inst.SUBOP10 == 60 /* andcx */) || (inst.SUBOP10 == 316 /* xorx */))
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{
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gpr.SetImmediate(a, 0);
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}
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else
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{
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PanicAlert("WTF!");
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}
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if (inst.Rc)
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ComputeRC(a);
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}
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else
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{
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if (inst.SUBOP10 == 28) // andx
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{
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AND(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else if (inst.SUBOP10 == 476) // nandx
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{
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AND(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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MVN(gpr.R(a), gpr.R(a));
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}
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else if (inst.SUBOP10 == 60) // andcx
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{
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BIC(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else if (inst.SUBOP10 == 444) // orx
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{
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ORR(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else if (inst.SUBOP10 == 124) // norx
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{
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ORR(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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MVN(gpr.R(a), gpr.R(a));
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}
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else if (inst.SUBOP10 == 412) // orcx
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{
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ORN(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else if (inst.SUBOP10 == 316) // xorx
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{
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EOR(gpr.R(a), gpr.R(s), gpr.R(b), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else if (inst.SUBOP10 == 284) // eqvx
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{
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EON(gpr.R(a), gpr.R(b), gpr.R(s), ArithOption(gpr.R(a), ST_LSL, 0));
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}
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else
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{
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PanicAlert("WTF!");
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}
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if (inst.Rc)
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ComputeRC(a);
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}
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}
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@ -51,19 +51,19 @@ static GekkoOPTemplate primarytable[] =
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{11, &JitArm64::FallBackToInterpreter}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
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{12, &JitArm64::FallBackToInterpreter}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
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{13, &JitArm64::FallBackToInterpreter}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}},
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{14, &JitArm64::FallBackToInterpreter}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
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{15, &JitArm64::FallBackToInterpreter}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
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{14, &JitArm64::arith_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
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{15, &JitArm64::arith_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
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{20, &JitArm64::FallBackToInterpreter}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
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{21, &JitArm64::FallBackToInterpreter}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
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{23, &JitArm64::FallBackToInterpreter}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
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{24, &JitArm64::FallBackToInterpreter}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{25, &JitArm64::FallBackToInterpreter}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{26, &JitArm64::FallBackToInterpreter}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{27, &JitArm64::FallBackToInterpreter}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{28, &JitArm64::FallBackToInterpreter}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
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{29, &JitArm64::FallBackToInterpreter}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
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{24, &JitArm64::arith_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{25, &JitArm64::arith_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{26, &JitArm64::arith_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{27, &JitArm64::arith_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
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{28, &JitArm64::arith_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
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{29, &JitArm64::arith_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
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{32, &JitArm64::FallBackToInterpreter}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
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{33, &JitArm64::FallBackToInterpreter}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
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@ -181,14 +181,14 @@ static GekkoOPTemplate table19[] =
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static GekkoOPTemplate table31[] =
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{
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{28, &JitArm64::FallBackToInterpreter}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{60, &JitArm64::FallBackToInterpreter}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{444, &JitArm64::FallBackToInterpreter}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{124, &JitArm64::FallBackToInterpreter}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{316, &JitArm64::FallBackToInterpreter}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{412, &JitArm64::FallBackToInterpreter}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{476, &JitArm64::FallBackToInterpreter}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{284, &JitArm64::FallBackToInterpreter}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{28, &JitArm64::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{60, &JitArm64::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{444, &JitArm64::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{124, &JitArm64::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{316, &JitArm64::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{412, &JitArm64::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{476, &JitArm64::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{284, &JitArm64::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
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{0, &JitArm64::FallBackToInterpreter}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
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{32, &JitArm64::FallBackToInterpreter}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
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{26, &JitArm64::FallBackToInterpreter}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
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