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Merge pull request #7060 from lioncash/reg 

Gekko: Make register constructors explicit where applicable
This commit is contained in:
Léo Lam 2018-06-03 21:04:34 +02:00 committed by GitHub
parent c22205cd7e 06056d4f45
commit 47bf809796
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 14 additions and 14 deletions
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18
Source/Core/Core/PowerPC/Gekko.h
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@ -322,7 +322,7 @@ union UGQR
u32 Hex = 0; u32 Hex = 0;
UGQR() = default; UGQR() = default;
UGQR(u32 hex_) : Hex{hex_} {} explicit UGQR(u32 hex_) : Hex{hex_} {}
}; };
#define XER_CA_SHIFT 29 #define XER_CA_SHIFT 29
@ -346,7 +346,7 @@ union UReg_XER
u32 Hex = 0; u32 Hex = 0;
UReg_XER() = default; UReg_XER() = default;
UReg_XER(u32 hex_) : Hex{hex_} {} explicit UReg_XER(u32 hex_) : Hex{hex_} {}
}; };
// Machine State Register // Machine State Register
@ -546,7 +546,7 @@ union UReg_HID2
u32 Hex = 0; u32 Hex = 0;
UReg_HID2() = default; UReg_HID2() = default;
UReg_HID2(u32 hex_) : Hex{hex_} {} explicit UReg_HID2(u32 hex_) : Hex{hex_} {}
}; };
// Hardware Implementation-Dependent Register 4 // Hardware Implementation-Dependent Register 4
@ -569,7 +569,7 @@ union UReg_HID4
u32 Hex = 0; u32 Hex = 0;
UReg_HID4() = default; UReg_HID4() = default;
UReg_HID4(u32 hex_) : Hex{hex_} {} explicit UReg_HID4(u32 hex_) : Hex{hex_} {}
}; };
// SPR1 - Page Table format // SPR1 - Page Table format
@ -632,7 +632,7 @@ union UReg_WPAR
u32 Hex = 0; u32 Hex = 0;
UReg_WPAR() = default; UReg_WPAR() = default;
UReg_WPAR(u32 hex_) : Hex{hex_} {} explicit UReg_WPAR(u32 hex_) : Hex{hex_} {}
}; };
// Direct Memory Access Upper register // Direct Memory Access Upper register
@ -646,7 +646,7 @@ union UReg_DMAU
u32 Hex = 0; u32 Hex = 0;
UReg_DMAU() = default; UReg_DMAU() = default;
UReg_DMAU(u32 hex_) : Hex{hex_} {} explicit UReg_DMAU(u32 hex_) : Hex{hex_} {}
}; };
// Direct Memory Access Lower (DMAL) register // Direct Memory Access Lower (DMAL) register
@ -663,7 +663,7 @@ union UReg_DMAL
u32 Hex = 0; u32 Hex = 0;
UReg_DMAL() = default; UReg_DMAL() = default;
UReg_DMAL(u32 hex_) : Hex{hex_} {} explicit UReg_DMAL(u32 hex_) : Hex{hex_} {}
}; };
union UReg_BAT_Up union UReg_BAT_Up
@ -679,7 +679,7 @@ union UReg_BAT_Up
u32 Hex = 0; u32 Hex = 0;
UReg_BAT_Up() = default; UReg_BAT_Up() = default;
UReg_BAT_Up(u32 hex_) : Hex{hex_} {} explicit UReg_BAT_Up(u32 hex_) : Hex{hex_} {}
}; };
union UReg_BAT_Lo union UReg_BAT_Lo
@ -695,7 +695,7 @@ union UReg_BAT_Lo
u32 Hex = 0; u32 Hex = 0;
UReg_BAT_Lo() = default; UReg_BAT_Lo() = default;
UReg_BAT_Lo(u32 hex_) : Hex{hex_} {} explicit UReg_BAT_Lo(u32 hex_) : Hex{hex_} {}
}; };
union UReg_PTE union UReg_PTE

2
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
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@ -398,7 +398,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
break; break;
case SPR_XER: case SPR_XER:
PowerPC::SetXER(rSPR(index)); PowerPC::SetXER(UReg_XER{rSPR(index)});
break; break;
case SPR_DBAT0L: case SPR_DBAT0L:

6
Source/Core/Core/PowerPC/MMU.cpp
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@ -1170,9 +1170,9 @@ static void UpdateBATs(BatTable& bat_table, u32 base_spr)
// TODO: Check how hardware reacts to invalid BATs (bad mask etc). // TODO: Check how hardware reacts to invalid BATs (bad mask etc).
for (int i = 0; i < 4; ++i) for (int i = 0; i < 4; ++i)
{ {
u32 spr = base_spr + i * 2; const u32 spr = base_spr + i * 2;
UReg_BAT_Up batu = PowerPC::ppcState.spr[spr]; const UReg_BAT_Up batu{ppcState.spr[spr]};
UReg_BAT_Lo batl = PowerPC::ppcState.spr[spr + 1]; const UReg_BAT_Lo batl{ppcState.spr[spr + 1]};
if (batu.VS == 0 && batu.VP == 0) if (batu.VS == 0 && batu.VP == 0)
continue; continue;

2
Source/Core/Core/PowerPC/PowerPC.h
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@ -303,7 +303,7 @@ inline UReg_XER GetXER()
xer |= PowerPC::ppcState.xer_stringctrl; xer |= PowerPC::ppcState.xer_stringctrl;
xer |= PowerPC::ppcState.xer_ca << XER_CA_SHIFT; xer |= PowerPC::ppcState.xer_ca << XER_CA_SHIFT;
xer |= PowerPC::ppcState.xer_so_ov << XER_OV_SHIFT; xer |= PowerPC::ppcState.xer_so_ov << XER_OV_SHIFT;
return xer; return UReg_XER{xer};
} }
inline void SetXER(UReg_XER new_xer) inline void SetXER(UReg_XER new_xer)