Merge pull request #415 from magumagu/memory-cleanup
Memory code cleanup
This commit is contained in:
commit
4758b362c3
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@ -237,7 +237,7 @@ void Memset(const u32 _Address, const u8 _iValue, const u32 _iLength)
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void DMA_LCToMemory(const u32 _MemAddr, const u32 _CacheAddr, const u32 _iNumBlocks)
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{
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const u8 *src = GetCachePtr() + (_CacheAddr & 0x3FFFF);
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const u8 *src = m_pL1Cache + (_CacheAddr & 0x3FFFF);
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u8 *dst = GetPointer(_MemAddr);
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if ((dst != nullptr) && (src != nullptr) && (_MemAddr & 3) == 0 && (_CacheAddr & 3) == 0)
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@ -257,7 +257,7 @@ void DMA_LCToMemory(const u32 _MemAddr, const u32 _CacheAddr, const u32 _iNumBlo
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void DMA_MemoryToLC(const u32 _CacheAddr, const u32 _MemAddr, const u32 _iNumBlocks)
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{
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const u8 *src = GetPointer(_MemAddr);
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u8 *dst = GetCachePtr() + (_CacheAddr & 0x3FFFF);
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u8 *dst = m_pL1Cache + (_CacheAddr & 0x3FFFF);
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if ((dst != nullptr) && (src != nullptr) && (_MemAddr & 3) == 0 && (_CacheAddr & 3) == 0)
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{
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@ -333,7 +333,7 @@ u8 *GetPointer(const u32 _Address)
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case 0xe:
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if (_Address < (0xE0000000 + L1_CACHE_SIZE))
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return GetCachePtr() + (_Address & L1_CACHE_MASK);
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return m_pL1Cache + (_Address & L1_CACHE_MASK);
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else
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break;
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@ -95,17 +95,6 @@ void WriteUnchecked_U32(const u32 _Data, const u32 _Address);
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bool IsRAMAddress(const u32 addr, bool allow_locked_cache = false, bool allow_fake_vmem = false);
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inline u8* GetCachePtr() {return m_pL1Cache;}
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inline u8* GetMainRAMPtr() {return m_pRAM;}
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inline u32 ReadFast32(const u32 _Address)
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{
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#if _ARCH_32
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return Common::swap32(*(u32 *)(base + (_Address & MEMVIEW32_MASK))); // ReadUnchecked_U32(_Address);
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#else
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return Common::swap32(*(u32 *)(base + _Address));
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#endif
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}
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// used by interpreter to read instructions, uses iCache
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u32 Read_Opcode(const u32 _Address);
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// this is used by Debugger a lot.
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@ -115,11 +104,6 @@ u32 Read_Instruction(const u32 _Address);
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// For use by emulator
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// Read and write functions
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#define NUMHWMEMFUN 64
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#define HWSHIFT 10
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#define HW_MASK 0x3FF
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u8 Read_U8(const u32 _Address);
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u16 Read_U16(const u32 _Address);
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u32 Read_U32(const u32 _Address);
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@ -133,9 +117,6 @@ double Read_F64(const u32 _Address);
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u32 Read_U8_ZX(const u32 _Address);
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u32 Read_U16_ZX(const u32 _Address);
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// used by JIT (Jit64::lXz)
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u32 EFB_Read(const u32 addr);
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void Write_U8(const u8 _Data, const u32 _Address);
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void Write_U16(const u16 _Data, const u32 _Address);
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void Write_U32(const u32 _Data, const u32 _Address);
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@ -148,7 +129,6 @@ void Write_U64_Swap(const u64 _Data, const u32 _Address);
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// Useful helper functions, used by ARM JIT
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void Write_F64(const double _Data, const u32 _Address);
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void WriteHW_U32(const u32 _Data, const u32 _Address);
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void GetString(std::string& _string, const u32 _Address);
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void WriteBigEData(const u8 *_pData, const u32 _Address, const size_t size);
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@ -169,9 +149,6 @@ enum XCheckTLBFlag
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};
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u32 TranslateAddress(u32 _Address, XCheckTLBFlag _Flag);
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void InvalidateTLBEntry(u32 _Address);
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void GenerateDSIException(u32 _EffectiveAdress, bool _bWrite);
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void GenerateISIException(u32 _EffectiveAdress);
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extern u32 pagetable_base;
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extern u32 pagetable_hashmask;
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};
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@ -71,7 +71,7 @@ inline u64 bswap(u64 val) {return Common::swap64(val);}
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// Nasty but necessary. Super Mario Galaxy pointer relies on this stuff.
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u32 EFB_Read(const u32 addr)
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static u32 EFB_Read(const u32 addr)
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{
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u32 var = 0;
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// Convert address to coordinates. It's possible that this should be done
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@ -90,6 +90,8 @@ u32 EFB_Read(const u32 addr)
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return var;
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}
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static void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite);
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template <typename T>
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inline void ReadFromHardware(T &_var, const u32 em_address, const u32 effective_address, Memory::XCheckTLBFlag flag)
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{
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@ -232,6 +234,9 @@ inline void WriteToHardware(u32 em_address, const T data, u32 effective_address,
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/* These functions are primarily called by the Interpreter functions and are routed to the correct
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location through ReadFromHardware and WriteToHardware */
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// ----------------
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static void GenerateISIException(u32 effective_address);
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u32 Read_Opcode(u32 _Address)
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{
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if (_Address == 0x00000000)
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@ -550,7 +555,7 @@ union UPTE2
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u32 Hex;
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};
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void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite)
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static void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite)
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{
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if (_bWrite)
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PowerPC::ppcState.spr[SPR_DSISR] = PPC_EXC_DSISR_PAGE | PPC_EXC_DSISR_STORE;
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@ -563,7 +568,7 @@ void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite)
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}
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void GenerateISIException(u32 _EffectiveAddress)
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static void GenerateISIException(u32 _EffectiveAddress)
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{
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// Address of instruction could not be translated
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NPC = _EffectiveAddress;
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@ -211,7 +211,6 @@ namespace JitInterface
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u32 Read_Opcode_JIT(u32 _Address)
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{
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#ifdef FAST_ICACHE
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if (bMMU && !bFakeVMEM && (_Address & Memory::ADDR_MASK_MEM1))
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{
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_Address = Memory::TranslateAddress(_Address, Memory::FLAG_OPCODE);
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@ -228,9 +227,6 @@ namespace JitInterface
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inst = Memory::ReadUnchecked_U32(_Address);
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else
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inst = PowerPC::ppcState.iCache.ReadInstruction(_Address);
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#else
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u32 inst = Memory::ReadUnchecked_U32(_Address);
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#endif
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return inst;
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}
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@ -59,11 +59,9 @@ namespace PowerPC
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{
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memset(valid, 0, sizeof(valid));
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memset(plru, 0, sizeof(plru));
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#ifdef FAST_ICACHE
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memset(lookup_table, 0xff, sizeof(lookup_table));
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memset(lookup_table_ex, 0xff, sizeof(lookup_table_ex));
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memset(lookup_table_vmem, 0xff, sizeof(lookup_table_vmem));
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#endif
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JitInterface::ClearSafe();
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}
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@ -83,7 +81,6 @@ namespace PowerPC
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return;
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// invalidates the whole set
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u32 set = (addr >> 5) & 0x7f;
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#ifdef FAST_ICACHE
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for (int i = 0; i < 8; i++)
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if (valid[set] & (1<<i))
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{
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@ -94,7 +91,6 @@ namespace PowerPC
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else
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lookup_table[((tags[set][i] << 7) | set) & 0xfffff] = 0xff;
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}
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#endif
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valid[set] = 0;
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JitInterface::InvalidateICache(addr & ~0x1f, 32);
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}
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@ -105,7 +101,7 @@ namespace PowerPC
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return Memory::ReadUnchecked_U32(addr);
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u32 set = (addr >> 5) & 0x7f;
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u32 tag = addr >> 12;
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#ifdef FAST_ICACHE
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u32 t;
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if (addr & ICACHE_VMEM_BIT)
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{
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@ -119,15 +115,7 @@ namespace PowerPC
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{
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t = lookup_table[(addr>>5) & 0xfffff];
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}
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#else
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u32 t = 0xff;
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for (u32 i = 0; i < 8; i++)
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if (tags[set][i] == tag && (valid[set] & (1<<i)))
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{
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t = i;
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break;
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}
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#endif
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if (t == 0xff) // load to the cache
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{
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if (HID0.ILOCK) // instruction cache is locked
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@ -140,7 +128,6 @@ namespace PowerPC
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// load
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u8 *p = Memory::GetPointer(addr & ~0x1f);
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memcpy(data[set][t], p, 32);
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#ifdef FAST_ICACHE
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if (valid[set] & (1<<t))
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{
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if (tags[set][t] & (ICACHE_VMEM_BIT >> 12))
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@ -157,7 +144,6 @@ namespace PowerPC
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lookup_table_ex[(addr>>5) & 0x1fffff] = t;
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else
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lookup_table[(addr>>5) & 0xfffff] = t;
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#endif
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tags[set][t] = tag;
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valid[set] |= 1<<t;
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}
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@ -6,8 +6,6 @@
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#include "Common/CommonTypes.h"
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#define FAST_ICACHE
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namespace PowerPC
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{
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@ -29,11 +27,9 @@ namespace PowerPC
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u32 way_from_valid[255];
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u32 way_from_plru[128];
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#ifdef FAST_ICACHE
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u8 lookup_table[1<<20];
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u8 lookup_table_ex[1<<21];
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u8 lookup_table_vmem[1<<20];
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#endif
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InstructionCache();
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u32 ReadInstruction(u32 addr);
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