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LLE JIT: 

* Optimised out the R11 ImmPtr instructions
* Made the whitespacing a little more consistent
* Disabled block linking while it is being reworked

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6688 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau 2010-12-30 00:10:18 +00:00
parent 98752f2a1e
commit 469e81e2fd
9 changed files with 362 additions and 307 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
Source/Core/DSPCore/Src/DSPEmitter.cpp
View File

@ -33,6 +33,7 @@ using namespace Gen;
const u8 *stubEntryPoint; const u8 *stubEntryPoint;
u16 blocksCompiled; u16 blocksCompiled;
u16 unresolvedCalls; u16 unresolvedCalls;
u16 unresolvedCallsThisBlock;
DSPEmitter::DSPEmitter() : storeIndex(-1), storeIndex2(-1) DSPEmitter::DSPEmitter() : storeIndex(-1), storeIndex2(-1)
{ {
@ -105,7 +106,7 @@ void DSPEmitter::checkExceptions(u32 retval)
// ABI_RestoreStack(0); // ABI_RestoreStack(0);
ABI_PopAllCalleeSavedRegsAndAdjustStack(); ABI_PopAllCalleeSavedRegsAndAdjustStack();
MOV(32,R(EAX),Imm32(retval)); MOV(32, R(EAX), Imm32(retval));
RET(); RET();
SetJumpTarget(skipCheck); SetJumpTarget(skipCheck);
@ -127,7 +128,9 @@ void DSPEmitter::Default(UDSPInstruction inst)
} }
// Fall back to interpreter // Fall back to interpreter
SaveDSPRegs();
ABI_CallFunctionC16((void*)opTable[inst]->intFunc, inst); ABI_CallFunctionC16((void*)opTable[inst]->intFunc, inst);
LoadDSPRegs();
} }
void DSPEmitter::EmitInstruction(UDSPInstruction inst) void DSPEmitter::EmitInstruction(UDSPInstruction inst)
@ -140,8 +143,10 @@ void DSPEmitter::EmitInstruction(UDSPInstruction inst)
if ((inst >> 12) == 0x3) { if ((inst >> 12) == 0x3) {
if (! extOpTable[inst & 0x7F]->jitFunc) { if (! extOpTable[inst & 0x7F]->jitFunc) {
// Fall back to interpreter // Fall back to interpreter
SaveDSPRegs();
ABI_CallFunctionC16((void*)extOpTable[inst & 0x7F]->intFunc, inst); ABI_CallFunctionC16((void*)extOpTable[inst & 0x7F]->intFunc, inst);
INFO_LOG(DSPLLE,"Instruction not JITed(ext part): %04x\n",inst); LoadDSPRegs();
INFO_LOG(DSPLLE, "Instruction not JITed(ext part): %04x\n", inst);
ext_is_jit = false; ext_is_jit = false;
} else { } else {
(this->*extOpTable[inst & 0x7F]->jitFunc)(inst); (this->*extOpTable[inst & 0x7F]->jitFunc)(inst);
@ -150,8 +155,10 @@ void DSPEmitter::EmitInstruction(UDSPInstruction inst)
} else { } else {
if (!extOpTable[inst & 0xFF]->jitFunc) { if (!extOpTable[inst & 0xFF]->jitFunc) {
// Fall back to interpreter // Fall back to interpreter
SaveDSPRegs();
ABI_CallFunctionC16((void*)extOpTable[inst & 0xFF]->intFunc, inst); ABI_CallFunctionC16((void*)extOpTable[inst & 0xFF]->intFunc, inst);
INFO_LOG(DSPLLE,"Instruction not JITed(ext part): %04x\n",inst); LoadDSPRegs();
INFO_LOG(DSPLLE, "Instruction not JITed(ext part): %04x\n", inst);
ext_is_jit = false; ext_is_jit = false;
} else { } else {
(this->*extOpTable[inst & 0xFF]->jitFunc)(inst); (this->*extOpTable[inst & 0xFF]->jitFunc)(inst);
@ -163,7 +170,7 @@ void DSPEmitter::EmitInstruction(UDSPInstruction inst)
// Main instruction // Main instruction
if (!opTable[inst]->jitFunc) { if (!opTable[inst]->jitFunc) {
Default(inst); Default(inst);
INFO_LOG(DSPLLE,"Instruction not JITed(main part): %04x\n",inst); INFO_LOG(DSPLLE, "Instruction not JITed(main part): %04x\n", inst);
} }
else else
{ {
@ -175,7 +182,9 @@ void DSPEmitter::EmitInstruction(UDSPInstruction inst)
if (!ext_is_jit) { if (!ext_is_jit) {
//need to call the online cleanup function because //need to call the online cleanup function because
//the writeBackLog gets populated at runtime //the writeBackLog gets populated at runtime
SaveDSPRegs();
ABI_CallFunction((void*)::applyWriteBackLog); ABI_CallFunction((void*)::applyWriteBackLog);
LoadDSPRegs();
} else { } else {
popExtValueToReg(); popExtValueToReg();
} }
@ -189,8 +198,7 @@ void DSPEmitter::unknown_instruction(UDSPInstruction inst)
void DSPEmitter::ClearCallFlag() void DSPEmitter::ClearCallFlag()
{ {
DSPAnalyzer::code_flags[startAddr] &= ~DSPAnalyzer::CODE_CALL; --unresolvedCallsThisBlock;
--unresolvedCalls;
} }
void DSPEmitter::Compile(int start_addr) void DSPEmitter::Compile(int start_addr)
@ -198,11 +206,12 @@ void DSPEmitter::Compile(int start_addr)
// Remember the current block address for later // Remember the current block address for later
startAddr = start_addr; startAddr = start_addr;
blocksCompiled++; blocksCompiled++;
unresolvedCallsThisBlock = 0;
// If the number of unresolved calls exceeds 50, there is a critical // If the number of unresolved calls exceeds 8, there is a critical
// block that probably cannot be resolved. If this occurs, quit linking // block that probably cannot be resolved. If this occurs, quit linking
// blocks. Currently occurs in the zelda ucode. // blocks. Currently occurs in the zelda ucode.
if (unresolvedCalls <= 50) if (unresolvedCalls <= 8)
{ {
// After every 10 blocks, clear out the blocks that have unresolved // After every 10 blocks, clear out the blocks that have unresolved
// calls, and reattempt relinking. // calls, and reattempt relinking.
@ -219,6 +228,7 @@ void DSPEmitter::Compile(int start_addr)
} }
// Reset and reattempt relinking // Reset and reattempt relinking
blocksCompiled = 0; blocksCompiled = 0;
unresolvedCalls = 0;
} }
} }
@ -269,6 +279,8 @@ void DSPEmitter::Compile(int start_addr)
bool fixup_pc = false; bool fixup_pc = false;
blockSize[start_addr] = 0; blockSize[start_addr] = 0;
LoadDSPRegs();
while (compilePC < start_addr + MAX_BLOCK_SIZE) while (compilePC < start_addr + MAX_BLOCK_SIZE)
{ {
checkExceptions(blockSize[start_addr]); checkExceptions(blockSize[start_addr]);
@ -277,10 +289,11 @@ void DSPEmitter::Compile(int start_addr)
const DSPOPCTemplate *opcode = GetOpTemplate(inst); const DSPOPCTemplate *opcode = GetOpTemplate(inst);
// Scan for CALL's to delay block link. TODO: Scan for J_CC after it is jitted. // Scan for CALL's to delay block link. TODO: Scan for J_CC after it is jitted.
if (opcode->jitFunc && (opcode->opcode >= 0x02b0 && opcode->opcode <= 0x02bf)) if (opcode->jitFunc &&
((opcode->opcode >= 0x0290 && opcode->opcode <= 0x029f) ||
(opcode->opcode >= 0x02b0 && opcode->opcode <= 0x02bf)))
{ {
DSPAnalyzer::code_flags[start_addr] |= DSPAnalyzer::CODE_CALL; ++unresolvedCallsThisBlock;
++unresolvedCalls;
} }
EmitInstruction(inst); EmitInstruction(inst);
@ -298,7 +311,7 @@ void DSPEmitter::Compile(int start_addr)
MOVZX(32, 16, EAX, M(&(g_dsp.r.st[2]))); MOVZX(32, 16, EAX, M(&(g_dsp.r.st[2])));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[2]))); MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[2])));
#endif #endif
CMP(32, R(EAX), Imm32(0)); CMP(32, R(EAX), Imm32(0));
FixupBranch rLoopAddressExit = J_CC(CC_LE, true); FixupBranch rLoopAddressExit = J_CC(CC_LE, true);
@ -306,7 +319,7 @@ void DSPEmitter::Compile(int start_addr)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r.st[3])); MOVZX(32, 16, EAX, M(&g_dsp.r.st[3]));
#else #else
MOVZX(32, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[3]))); MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[3])));
#endif #endif
CMP(32, R(EAX), Imm32(0)); CMP(32, R(EAX), Imm32(0));
FixupBranch rLoopCounterExit = J_CC(CC_LE, true); FixupBranch rLoopCounterExit = J_CC(CC_LE, true);
@ -398,8 +411,17 @@ void DSPEmitter::Compile(int start_addr)
// Mark this block as a linkable destination if it does not contain // Mark this block as a linkable destination if it does not contain
// any unresolved CALL's // any unresolved CALL's
if (!(DSPAnalyzer::code_flags[start_addr] & DSPAnalyzer::CODE_CALL)) if (unresolvedCallsThisBlock == 0)
{
DSPAnalyzer::code_flags[start_addr] &= ~DSPAnalyzer::CODE_CALL;
blockLinks[start_addr] = (CompiledCode)blockLinkEntry; blockLinks[start_addr] = (CompiledCode)blockLinkEntry;
}
else
{
DSPAnalyzer::code_flags[start_addr] |= DSPAnalyzer::CODE_CALL;
blockLinks[start_addr] = 0;
++unresolvedCalls;
}
if (blockSize[start_addr] == 0) if (blockSize[start_addr] == 0)
{ {
@ -409,6 +431,8 @@ void DSPEmitter::Compile(int start_addr)
blockSize[start_addr] = 1; blockSize[start_addr] = 1;
} }
SaveDSPRegs();
// ABI_RestoreStack(0); // ABI_RestoreStack(0);
ABI_PopAllCalleeSavedRegsAndAdjustStack(); ABI_PopAllCalleeSavedRegsAndAdjustStack();
if (DSPAnalyzer::code_flags[start_addr] & DSPAnalyzer::CODE_IDLE_SKIP) if (DSPAnalyzer::code_flags[start_addr] & DSPAnalyzer::CODE_IDLE_SKIP)
@ -459,8 +483,8 @@ void DSPEmitter::CompileDispatcher()
#ifdef _M_IX86 #ifdef _M_IX86
TEST(8, M(&g_dsp.cr), Imm8(CR_HALT)); TEST(8, M(&g_dsp.cr), Imm8(CR_HALT));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.cr)); MOV(64, R(RAX), ImmPtr(&g_dsp.cr));
TEST(8, MatR(R11), Imm8(CR_HALT)); TEST(8, MatR(RAX), Imm8(CR_HALT));
#endif #endif
FixupBranch halt = J_CC(CC_NE); FixupBranch halt = J_CC(CC_NE);

3
Source/Core/DSPCore/Src/DSPEmitter.h
View File

@ -265,6 +265,9 @@ private:
// Counts down. // Counts down.
// int cycles; // int cycles;
void LoadDSPRegs();
void SaveDSPRegs();
void Update_SR_Register(Gen::X64Reg val = Gen::EAX); void Update_SR_Register(Gen::X64Reg val = Gen::EAX);
void ToMask(Gen::X64Reg value_reg = Gen::EDI); void ToMask(Gen::X64Reg value_reg = Gen::EDI);

16
Source/Core/DSPCore/Src/Jit/DSPJitArithmetic.cpp
View File

@ -98,7 +98,7 @@ void DSPEmitter::andcf(const UDSPInstruction opc)
// g_dsp.r.sr &= ~SR_LOGIC_ZERO; // g_dsp.r.sr &= ~SR_LOGIC_ZERO;
AND(16, R(RAX), Imm16(imm)); AND(16, R(RAX), Imm16(imm));
CMP(16, R(RAX), Imm16(imm)); CMP(16, R(RAX), Imm16(imm));
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
FixupBranch notLogicZero = J_CC(CC_NE); FixupBranch notLogicZero = J_CC(CC_NE);
OR(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(SR_LOGIC_ZERO)); OR(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(SR_LOGIC_ZERO));
FixupBranch exit = J(); FixupBranch exit = J();
@ -135,7 +135,7 @@ void DSPEmitter::andf(const UDSPInstruction opc)
// else // else
// g_dsp.r.sr &= ~SR_LOGIC_ZERO; // g_dsp.r.sr &= ~SR_LOGIC_ZERO;
TEST(16, R(RAX), Imm16(imm)); TEST(16, R(RAX), Imm16(imm));
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
FixupBranch notLogicZero = J_CC(CC_NE); FixupBranch notLogicZero = J_CC(CC_NE);
OR(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(SR_LOGIC_ZERO)); OR(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(SR_LOGIC_ZERO));
FixupBranch exit = J(); FixupBranch exit = J();
@ -606,12 +606,12 @@ void DSPEmitter::addr(const UDSPInstruction opc)
u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0;
u16 *sregp = reg_ptr(sreg); u16 *sregp = reg_ptr(sreg);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// s64 acc = dsp_get_long_acc(dreg); // s64 acc = dsp_get_long_acc(dreg);
get_long_acc(dreg, RCX); get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX)); MOV(64, R(RAX), R(RCX));
// s64 ax = (s16)g_dsp.r[sreg]; // s64 ax = (s16)g_dsp.r[sreg];
MOVSX(64, 16, RDX, MDisp(R11, PtrOffset(sregp,&g_dsp.r))); MOVSX(64, 16, RDX, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
// ax <<= 16; // ax <<= 16;
SHL(64, R(RDX), Imm8(16)); SHL(64, R(RDX), Imm8(16));
// s64 res = acc + ax; // s64 res = acc + ax;
@ -941,8 +941,8 @@ void DSPEmitter::subr(const UDSPInstruction opc)
get_long_acc(dreg, RCX); get_long_acc(dreg, RCX);
MOV(64, R(RAX), R(RCX)); MOV(64, R(RAX), R(RCX));
// s64 ax = (s16)g_dsp.r[sreg]; // s64 ax = (s16)g_dsp.r[sreg];
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RDX, MDisp(R11, PtrOffset(sregp,&g_dsp.r))); MOVSX(64, 16, RDX, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
// ax <<= 16; // ax <<= 16;
SHL(64, R(RDX), Imm8(16)); SHL(64, R(RDX), Imm8(16));
// s64 res = acc - ax; // s64 res = acc - ax;
@ -1213,8 +1213,8 @@ void DSPEmitter::movr(const UDSPInstruction opc)
u16 *sregp = reg_ptr(sreg); u16 *sregp = reg_ptr(sreg);
// s64 acc = (s16)g_dsp.r[sreg]; // s64 acc = (s16)g_dsp.r[sreg];
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RAX, MDisp(R11, PtrOffset(sregp,&g_dsp.r))); MOVSX(64, 16, RAX, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
// acc <<= 16; // acc <<= 16;
SHL(64, R(RAX), Imm8(16)); SHL(64, R(RAX), Imm8(16));
// acc &= ~0xffff; // acc &= ~0xffff;

98
Source/Core/DSPCore/Src/Jit/DSPJitBranch.cpp
View File

@ -168,43 +168,43 @@ void r_jcc(const UDSPInstruction opc, DSPEmitter& emitter)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest)); emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest));
// Jump directly to the called block if it has already been compiled. (Not working) // Jump directly to the called block if it has already been compiled.
//if (emitter.blockLinks[dest]) if (emitter.blockLinks[dest])
//{ {
// // Check if we have enough cycles to execute the next block // Check if we have enough cycles to execute the next block
// emitter.MOV(16, R(ESI), M(&cyclesLeft)); emitter.MOV(16, R(ESI), M(&cyclesLeft));
// emitter.CMP(16, R(ESI),Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest])); emitter.CMP(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest]));
// FixupBranch notEnoughCycles = emitter.J_CC(CC_BE); FixupBranch notEnoughCycles = emitter.J_CC(CC_BE);
// emitter.SUB(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr])); emitter.SUB(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr]));
// emitter.MOV(16, M(&cyclesLeft), R(ESI)); emitter.MOV(16, M(&cyclesLeft), R(ESI));
// emitter.JMPptr(M(&emitter.blockLinks[dest])); emitter.JMPptr(M(&emitter.blockLinks[dest]));
// emitter.ClearCallFlag(); emitter.ClearCallFlag();
// emitter.SetJumpTarget(notEnoughCycles); emitter.SetJumpTarget(notEnoughCycles);
//} }
#else #else
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc))); emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
emitter.MOV(16, MatR(RAX), Imm16(dest)); emitter.MOV(16, MatR(RAX), Imm16(dest));
// Jump directly to the next block if it has already been compiled. (Not working) // Jump directly to the next block if it has already been compiled.
//if (emitter.blockLinks[dest]) if (emitter.blockLinks[dest])
//{ {
// // Check if we have enough cycles to execute the next block // Check if we have enough cycles to execute the next block
// emitter.MOV(64, R(R12), ImmPtr(&cyclesLeft)); //emitter.MOV(64, R(R12), ImmPtr(&cyclesLeft));
// emitter.MOV(16, R(RAX), MatR(R12)); //emitter.MOV(16, R(RAX), MatR(R12));
// emitter.CMP(16,R(RAX),Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest])); //emitter.CMP(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest]));
// FixupBranch notEnoughCycles = emitter.J_CC(CC_BE); //FixupBranch notEnoughCycles = emitter.J_CC(CC_BE);
// emitter.SUB(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr])); //emitter.SUB(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr]));
// emitter.MOV(16, MatR(R12), R(RAX)); //emitter.MOV(16, MatR(R12), R(RAX));
// emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest]))); //emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest])));
// emitter.JMPptr(R(RAX)); //emitter.JMPptr(R(RAX));
// emitter.ClearCallFlag(); //emitter.ClearCallFlag();
// emitter.SetJumpTarget(notEnoughCycles); //emitter.SetJumpTarget(notEnoughCycles);
//} }
#endif #endif
WriteBranchExit(emitter); WriteBranchExit(emitter);
} }
@ -271,16 +271,16 @@ void r_call(const UDSPInstruction opc, DSPEmitter& emitter)
if (emitter.blockLinks[dest]) if (emitter.blockLinks[dest])
{ {
// Check if we have enough cycles to execute the next block // Check if we have enough cycles to execute the next block
emitter.MOV(16, R(ESI), M(&cyclesLeft)); //emitter.MOV(16, R(ESI), M(&cyclesLeft));
emitter.CMP(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest])); //emitter.CMP(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest]));
FixupBranch notEnoughCycles = emitter.J_CC(CC_BE); //FixupBranch notEnoughCycles = emitter.J_CC(CC_BE);
emitter.SUB(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr])); //emitter.SUB(16, R(ESI), Imm16(emitter.blockSize[emitter.startAddr]));
emitter.MOV(16, M(&cyclesLeft), R(ESI)); //emitter.MOV(16, M(&cyclesLeft), R(ESI));
emitter.JMPptr(M(&emitter.blockLinks[dest])); //emitter.JMPptr(M(&emitter.blockLinks[dest]));
emitter.ClearCallFlag(); //emitter.ClearCallFlag();
emitter.SetJumpTarget(notEnoughCycles); //emitter.SetJumpTarget(notEnoughCycles);
} }
#else #else
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc))); emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
@ -292,7 +292,7 @@ void r_call(const UDSPInstruction opc, DSPEmitter& emitter)
// Check if we have enough cycles to execute the next block // Check if we have enough cycles to execute the next block
emitter.MOV(64, R(R12), ImmPtr(&cyclesLeft)); emitter.MOV(64, R(R12), ImmPtr(&cyclesLeft));
emitter.MOV(16, R(RAX), MatR(R12)); emitter.MOV(16, R(RAX), MatR(R12));
emitter.CMP(16,R(RAX), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest])); emitter.CMP(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr] + emitter.blockSize[dest]));
FixupBranch notEnoughCycles = emitter.J_CC(CC_BE); FixupBranch notEnoughCycles = emitter.J_CC(CC_BE);
emitter.SUB(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr])); emitter.SUB(16, R(RAX), Imm16(emitter.blockSize[emitter.startAddr]));
@ -427,8 +427,8 @@ void DSPEmitter::rti(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.sr), R(DX)); MOV(16, M(&g_dsp.r.sr), R(DX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, sr)), R(DX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), R(DX));
#endif #endif
// g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); // g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C);
dsp_reg_load_stack(DSP_STACK_C); dsp_reg_load_stack(DSP_STACK_C);
@ -473,9 +473,9 @@ void DSPEmitter::HandleLoop()
MOVZX(32, 16, EAX, M(&g_dsp.r.st[2])); MOVZX(32, 16, EAX, M(&g_dsp.r.st[2]));
MOVZX(32, 16, ECX, M(&g_dsp.r.st[3])); MOVZX(32, 16, ECX, M(&g_dsp.r.st[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[2]))); MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[2])));
MOVZX(32, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[3]))); MOVZX(32, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[3])));
#endif #endif
CMP(32, R(RCX), Imm32(0)); CMP(32, R(RCX), Imm32(0));
@ -487,8 +487,8 @@ void DSPEmitter::HandleLoop()
SUB(16, M(&(g_dsp.r.st[3])), Imm16(1)); SUB(16, M(&(g_dsp.r.st[3])), Imm16(1));
CMP(16, M(&(g_dsp.r.st[3])), Imm16(0)); CMP(16, M(&(g_dsp.r.st[3])), Imm16(0));
#else #else
SUB(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[3])), Imm16(1)); SUB(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[3])), Imm16(1));
CMP(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[3])), Imm16(0)); CMP(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[3])), Imm16(0));
#endif #endif
FixupBranch loadStack = J_CC(CC_LE, true); FixupBranch loadStack = J_CC(CC_LE, true);
@ -496,7 +496,7 @@ void DSPEmitter::HandleLoop()
MOVZX(32, 16, ECX, M(&(g_dsp.r.st[0]))); MOVZX(32, 16, ECX, M(&(g_dsp.r.st[0])));
MOV(16, M(&g_dsp.pc), R(RCX)); MOV(16, M(&g_dsp.pc), R(RCX));
#else #else
MOVZX(32, 16, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[0]))); MOVZX(32, 16, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[0])));
MOV(64, R(RAX), ImmPtr(&(g_dsp.pc))); MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
MOV(16, MatR(RAX), R(RCX)); MOV(16, MatR(RAX), R(RCX));
#endif #endif
@ -529,8 +529,8 @@ void DSPEmitter::loop(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EDX, M(regp)); MOVZX(32, 16, EDX, M(regp));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EDX, MDisp(R11,PtrOffset(regp, &g_dsp.r))); MOVZX(32, 16, EDX, MDisp(R11, PtrOffset(regp, &g_dsp.r)));
#endif #endif
u16 loop_pc = compilePC + 1; u16 loop_pc = compilePC + 1;
@ -600,8 +600,8 @@ void DSPEmitter::bloop(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EDX, M(regp)); MOVZX(32, 16, EDX, M(regp));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EDX, MDisp(R11,PtrOffset(regp, &g_dsp.r))); MOVZX(32, 16, EDX, MDisp(R11, PtrOffset(regp, &g_dsp.r)));
#endif #endif
u16 loop_pc = dsp_imem_read(compilePC + 1); u16 loop_pc = dsp_imem_read(compilePC + 1);

160
Source/Core/DSPCore/Src/Jit/DSPJitExtOps.cpp
View File

@ -98,9 +98,9 @@ void DSPEmitter::s(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
MOVZX(32, 16, ECX, M(sregp)); MOVZX(32, 16, ECX, M(sregp));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOVZX(64, 16, ECX, MDisp(R11,PtrOffset(sregp, &g_dsp.r))); MOVZX(64, 16, ECX, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
#endif #endif
// u16 val = g_dsp.r[src]; // u16 val = g_dsp.r[src];
dmem_write(); dmem_write();
@ -133,9 +133,9 @@ void DSPEmitter::sn(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
MOVZX(32, 16, ECX, M(sregp)); MOVZX(32, 16, ECX, M(sregp));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOVZX(64, 16, ECX, MDisp(R11,PtrOffset(sregp,&g_dsp.r))); MOVZX(64, 16, ECX, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
#endif #endif
dmem_write(); dmem_write();
increase_addr_reg(dreg); increase_addr_reg(dreg);
@ -160,8 +160,8 @@ void DSPEmitter::l(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(EAX), M(&g_dsp.r.sr)); MOV(16, R(EAX), M(&g_dsp.r.sr));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r.sr)); MOV(64, R(RAX), ImmPtr(&g_dsp.r.sr));
MOV(16, R(EAX), MatR(R11)); MOV(16, R(RAX), MatR(RAX));
#endif #endif
SHL(32, R(EAX), Imm8(16)); SHL(32, R(EAX), Imm8(16));
OR(32, R(EBX), R(EAX)); OR(32, R(EBX), R(EAX));
@ -189,8 +189,8 @@ void DSPEmitter::ln(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(EAX), M(&g_dsp.r.sr)); MOV(16, R(EAX), M(&g_dsp.r.sr));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r.sr)); MOV(64, R(RAX), ImmPtr(&g_dsp.r.sr));
MOV(16, R(EAX), MatR(R11)); MOV(16, R(RAX), MatR(RAX));
#endif #endif
SHL(32, R(EAX), Imm8(16)); SHL(32, R(EAX), Imm8(16));
OR(32, R(EBX), R(EAX)); OR(32, R(EBX), R(EAX));
@ -212,9 +212,9 @@ void DSPEmitter::ls(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -239,9 +239,9 @@ void DSPEmitter::lsn(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -265,9 +265,9 @@ void DSPEmitter::lsm(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -292,9 +292,9 @@ void DSPEmitter::lsnm(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[3]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -317,9 +317,9 @@ void DSPEmitter::sl(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[0]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[0])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -343,9 +343,9 @@ void DSPEmitter::sln(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[0]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[0])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -369,9 +369,9 @@ void DSPEmitter::slm(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[0]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[0])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -395,9 +395,9 @@ void DSPEmitter::slnm(const UDSPInstruction opc)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[0]));
MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m)); MOVZX(32, 16, ECX, M(&g_dsp.r.ac[sreg].m));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[0]))); MOVZX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[0])));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
#endif #endif
dmem_write(); dmem_write();
@ -431,9 +431,9 @@ void DSPEmitter::ld(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[sreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[sreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -455,16 +455,16 @@ void DSPEmitter::ld(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[dreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[dreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
CMP(16, R(ESI), R(EDI)); CMP(16, R(ESI), R(EDI));
FixupBranch not_equal = J_CC(CC_NE); FixupBranch not_equal = J_CC(CC_NE, true);
pushExtValueFromMem2(rreg + DSP_REG_AXL0, dreg); pushExtValueFromMem2(rreg + DSP_REG_AXL0, dreg);
FixupBranch after = J(); // else FixupBranch after = J(true); // else
SetJumpTarget(not_equal); SetJumpTarget(not_equal);
pushExtValueFromMem2(rreg + DSP_REG_AXL0, DSP_REG_AR3); pushExtValueFromMem2(rreg + DSP_REG_AXL0, DSP_REG_AR3);
SetJumpTarget(after); SetJumpTarget(after);
@ -491,9 +491,9 @@ void DSPEmitter::ldn(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[sreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[sreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -514,9 +514,9 @@ void DSPEmitter::ldn(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[dreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[dreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -550,9 +550,9 @@ void DSPEmitter::ldm(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[sreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[sreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -573,9 +573,9 @@ void DSPEmitter::ldm(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[dreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[dreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -609,9 +609,9 @@ void DSPEmitter::ldnm(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[sreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[sreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -632,9 +632,9 @@ void DSPEmitter::ldnm(const UDSPInstruction opc)
MOV(16, R(ESI), M(&g_dsp.r.ar[dreg])); MOV(16, R(ESI), M(&g_dsp.r.ar[dreg]));
MOV(16, R(EDI), M(&g_dsp.r.ar[3])); MOV(16, R(EDI), M(&g_dsp.r.ar[3]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(ESI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOV(16, R(ESI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
MOV(16, R(EDI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[3]))); MOV(16, R(EDI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[3])));
#endif #endif
SHR(16, R(ESI), Imm8(10)); SHR(16, R(ESI), Imm8(10));
SHR(16, R(EDI), Imm8(10)); SHR(16, R(EDI), Imm8(10));
@ -661,7 +661,7 @@ void DSPEmitter::pushExtValueFromReg(u16 dreg, u16 sreg) {
MOVZX(32, 16, EBX, M(sregp)); MOVZX(32, 16, EBX, M(sregp));
#else #else
MOV(64, R(RBX), ImmPtr(&g_dsp.r)); MOV(64, R(RBX), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EBX, MDisp(RBX,PtrOffset(sregp,&g_dsp.r))); MOVZX(32, 16, EBX, MDisp(RBX, PtrOffset(sregp, &g_dsp.r)));
#endif #endif
storeIndex = dreg; storeIndex = dreg;
} }
@ -671,8 +671,8 @@ void DSPEmitter::pushExtValueFromMem(u16 dreg, u16 sreg) {
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[sreg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[sreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
#endif #endif
dmem_read(); dmem_read();
MOVZX(32, 16, EBX, R(EAX)); MOVZX(32, 16, EBX, R(EAX));
@ -685,11 +685,11 @@ void DSPEmitter::pushExtValueFromMem2(u16 dreg, u16 sreg) {
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[sreg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[sreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, ECX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[sreg]))); MOVZX(64, 16, ECX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[sreg])));
#endif #endif
dmem_read(); dmem_read();
SHL(32,R(EAX),Imm8(16)); SHL(32, R(EAX), Imm8(16));
OR(32, R(EBX), R(EAX)); OR(32, R(EBX), R(EAX));
storeIndex2 = dreg; storeIndex2 = dreg;
@ -708,8 +708,8 @@ void DSPEmitter::popExtValueToReg() {
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(dregp), R(EBX)); MOV(16, M(dregp), R(EBX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,PtrOffset(dregp,&g_dsp.r)), R(EBX)); MOV(16, MDisp(R11, PtrOffset(dregp, &g_dsp.r)), R(EBX));
#endif #endif
if (storeIndex >= DSP_REG_ACM0 && storeIndex2 == -1) { if (storeIndex >= DSP_REG_ACM0 && storeIndex2 == -1) {
TEST(32, R(EBX), Imm32(SR_40_MODE_BIT << 16)); TEST(32, R(EBX), Imm32(SR_40_MODE_BIT << 16));
@ -719,17 +719,17 @@ void DSPEmitter::popExtValueToReg() {
// Sign extend into whole accum. // Sign extend into whole accum.
//u16 val = g_dsp.r[reg]; //u16 val = g_dsp.r[reg];
MOVSX(32, 16, EAX, R(EBX)); MOVSX(32, 16, EAX, R(EBX));
SHR(32,R(EAX),Imm8(16)); SHR(32, R(EAX), Imm8(16));
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16,M(&g_dsp.r.ac[storeIndex - DSP_REG_ACM0].h), MOV(16, M(&g_dsp.r.ac[storeIndex - DSP_REG_ACM0].h),
R(EAX)); R(EAX));
MOV(16,M(&g_dsp.r.ac[storeIndex - DSP_REG_ACM0].l), MOV(16, M(&g_dsp.r.ac[storeIndex - DSP_REG_ACM0].l),
Imm16(0)); Imm16(0));
#else #else
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[storeIndex - DSP_REG_ACM0].h)), R(EAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[storeIndex - DSP_REG_ACM0].h)), R(EAX));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[storeIndex - DSP_REG_ACM0].l)), Imm16(0)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[storeIndex - DSP_REG_ACM0].l)), Imm16(0));
#endif #endif
//} //}
SetJumpTarget(not_40bit); SetJumpTarget(not_40bit);
@ -739,13 +739,13 @@ void DSPEmitter::popExtValueToReg() {
storeIndex = -1; storeIndex = -1;
if (storeIndex2 != -1) { if (storeIndex2 != -1) {
SHR(32,R(EBX),Imm8(16)); SHR(32, R(EBX), Imm8(16));
u16 *dregp = reg_ptr(storeIndex2); u16 *dregp = reg_ptr(storeIndex2);
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(dregp), R(EBX)); MOV(16, M(dregp), R(EBX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,PtrOffset(dregp, &g_dsp.r)), R(EBX)); MOV(16, MDisp(R11, PtrOffset(dregp, &g_dsp.r)), R(EBX));
#endif #endif
} }
storeIndex2 = -1; storeIndex2 = -1;
@ -767,10 +767,18 @@ void DSPEmitter::zeroWriteBackLog(const UDSPInstruction opc)
if ((opc >> 12) == 0x3) { if ((opc >> 12) == 0x3) {
if (! extOpTable[opc & 0x7F]->jitFunc) if (! extOpTable[opc & 0x7F]->jitFunc)
{
SaveDSPRegs();
ABI_CallFunction((void*)::zeroWriteBackLog); ABI_CallFunction((void*)::zeroWriteBackLog);
LoadDSPRegs();
}
} else { } else {
if (! extOpTable[opc & 0xFF]->jitFunc) if (! extOpTable[opc & 0xFF]->jitFunc)
{
SaveDSPRegs();
ABI_CallFunction((void*)::zeroWriteBackLog); ABI_CallFunction((void*)::zeroWriteBackLog);
LoadDSPRegs();
}
} }
return; return;
} }

62
Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
View File

@ -40,9 +40,9 @@ void DSPEmitter::srs(const UDSPInstruction opc)
MOVZX(32, 16, ECX, M(regp)); MOVZX(32, 16, ECX, M(regp));
MOVZX(32, 8, EAX, M(&g_dsp.r.cr)); MOVZX(32, 8, EAX, M(&g_dsp.r.cr));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,PtrOffset(regp,&g_dsp.r))); MOVZX(64, 16, RCX, MDisp(R11, PtrOffset(regp, &g_dsp.r)));
MOVZX(64, 8, RAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, cr))); MOVZX(64, 8, RAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, cr)));
#endif #endif
SHL(16, R(EAX), Imm8(8)); SHL(16, R(EAX), Imm8(8));
OR(8, R(EAX), Imm8(opc & 0xFF)); OR(8, R(EAX), Imm8(opc & 0xFF));
@ -66,13 +66,13 @@ void DSPEmitter::lrs(const UDSPInstruction opc)
dmem_read(); dmem_read();
MOV(16, M(regp), R(EAX)); MOV(16, M(regp), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 8, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, cr))); MOVZX(64, 8, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, cr)));
SHL(16, R(ECX), Imm8(8)); SHL(16, R(ECX), Imm8(8));
OR(8, R(ECX), Imm8(opc & 0xFF)); OR(8, R(ECX), Imm8(opc & 0xFF));
dmem_read(); dmem_read();
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,PtrOffset(regp, &g_dsp.r)), R(RAX)); MOV(16, MDisp(R11, PtrOffset(regp, &g_dsp.r)), R(RAX));
#endif #endif
dsp_conditional_extend_accum(reg); dsp_conditional_extend_accum(reg);
} }
@ -197,8 +197,8 @@ void DSPEmitter::srr(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, RAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
#endif #endif
dmem_write(); dmem_write();
} }
@ -217,8 +217,8 @@ void DSPEmitter::srrd(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, RAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
#endif #endif
dmem_write(); dmem_write();
decrement_addr_reg(dreg); decrement_addr_reg(dreg);
@ -238,8 +238,8 @@ void DSPEmitter::srri(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, RAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
#endif #endif
dmem_write(); dmem_write();
increment_addr_reg(dreg); increment_addr_reg(dreg);
@ -259,8 +259,8 @@ void DSPEmitter::srrn(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[dreg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[dreg]))); MOVZX(64, 16, RAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[dreg])));
#endif #endif
dmem_write(); dmem_write();
increase_addr_reg(dreg); increase_addr_reg(dreg);
@ -278,15 +278,15 @@ void DSPEmitter::ilrr(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOVZX(64, 16, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
#endif #endif
imem_read(); imem_read();
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX)); MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX));
#endif #endif
dsp_conditional_extend_accum(dreg); dsp_conditional_extend_accum(dreg);
} }
@ -303,15 +303,15 @@ void DSPEmitter::ilrrd(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOVZX(64, 16, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
#endif #endif
imem_read(); imem_read();
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX)); MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX));
#endif #endif
dsp_conditional_extend_accum(dreg); dsp_conditional_extend_accum(dreg);
decrement_addr_reg(reg); decrement_addr_reg(reg);
@ -329,15 +329,15 @@ void DSPEmitter::ilrri(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOVZX(64, 16, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
#endif #endif
imem_read(); imem_read();
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX)); MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX));
#endif #endif
dsp_conditional_extend_accum(dreg); dsp_conditional_extend_accum(dreg);
increment_addr_reg(reg); increment_addr_reg(reg);
@ -356,15 +356,15 @@ void DSPEmitter::ilrrn(const UDSPInstruction opc)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg])); MOVZX(32, 16, ECX, M(&g_dsp.r.ar[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOVZX(64, 16, RCX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
#endif #endif
imem_read(); imem_read();
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX)); MOV(16, M(&g_dsp.r.ac[dreg].m), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[dreg].m)), R(RAX));
#endif #endif
dsp_conditional_extend_accum(dreg); dsp_conditional_extend_accum(dreg);
increase_addr_reg(reg); increase_addr_reg(reg);

94
Source/Core/DSPCore/Src/Jit/DSPJitMisc.cpp
View File

@ -36,27 +36,27 @@ void DSPEmitter::dsp_reg_stack_push(int stack_reg)
MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg])); MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg]));
#else #else
MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr)); MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
MOV(8, R(AL), MDisp(R10,stack_reg)); MOV(8, R(AL), MDisp(R10, stack_reg));
#endif #endif
ADD(8, R(AL), Imm8(1)); ADD(8, R(AL), Imm8(1));
AND(8, R(AL), Imm8(DSP_STACK_MASK)); AND(8, R(AL), Imm8(DSP_STACK_MASK));
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL)); MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL));
#else #else
MOV(8, MDisp(R10,stack_reg), R(AL)); MOV(8, MDisp(R10, stack_reg), R(AL));
#endif #endif
//g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]] = g_dsp.r[DSP_REG_ST0 + stack_reg]; //g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]] = g_dsp.r[DSP_REG_ST0 + stack_reg];
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(CX), M(&g_dsp.r.st[stack_reg])); MOV(16, R(CX), M(&g_dsp.r.st[stack_reg]));
MOVZX(32, 8, EAX, R(AL)); MOVZX(32, 8, EAX, R(AL));
MOV(16, MComplex(EAX,EAX,1,(u32)&g_dsp.reg_stack[stack_reg][0]), R(CX)); MOV(16, MComplex(EAX, EAX, 1, (u32)&g_dsp.reg_stack[stack_reg][0]), R(CX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(CX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[stack_reg]))); MOV(16, R(CX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[stack_reg])));
MOVZX(64, 8, RAX, R(AL)); MOVZX(64, 8, RAX, R(AL));
MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0])); MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0]));
MOV(16, MComplex(R10,RAX,2,0), R(CX)); MOV(16, MComplex(R10, RAX, 2, 0), R(CX));
#endif #endif
} }
@ -72,18 +72,18 @@ void DSPEmitter::dsp_reg_stack_pop(int stack_reg)
MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg])); MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg]));
#else #else
MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr)); MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
MOV(8, R(AL), MDisp(R10,stack_reg)); MOV(8, R(AL), MDisp(R10, stack_reg));
#endif #endif
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVZX(32, 8, EAX, R(AL)); MOVZX(32, 8, EAX, R(AL));
MOV(16, R(CX), MComplex(EAX,EAX,1,(u32)&g_dsp.reg_stack[stack_reg][0])); MOV(16, R(CX), MComplex(EAX, EAX, 1, (u32)&g_dsp.reg_stack[stack_reg][0]));
MOV(16, M(&g_dsp.r.st[stack_reg]), R(CX)); MOV(16, M(&g_dsp.r.st[stack_reg]), R(CX));
#else #else
MOVZX(64, 8, RAX, R(AL)); MOVZX(64, 8, RAX, R(AL));
MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0])); MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0]));
MOV(16, R(CX), MComplex(R10,RAX,2,0)); MOV(16, R(CX), MComplex(R10, RAX, 2, 0));
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[stack_reg])), R(CX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[stack_reg])), R(CX));
#endif #endif
//g_dsp.reg_stack_ptr[stack_reg]--; //g_dsp.reg_stack_ptr[stack_reg]--;
@ -94,7 +94,7 @@ void DSPEmitter::dsp_reg_stack_pop(int stack_reg)
MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL)); MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL));
#else #else
MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr)); MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
MOV(8, MDisp(R10,stack_reg), R(AL)); MOV(8, MDisp(R10, stack_reg), R(AL));
#endif #endif
} }
@ -109,8 +109,8 @@ void DSPEmitter::dsp_reg_store_stack(int stack_reg, Gen::X64Reg host_sreg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.st[stack_reg]), R(EDX)); MOV(16, M(&g_dsp.r.st[stack_reg]), R(EDX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[stack_reg])), R(EDX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[stack_reg])), R(EDX));
#endif #endif
} }
@ -120,8 +120,8 @@ void DSPEmitter::dsp_reg_load_stack(int stack_reg, Gen::X64Reg host_dreg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(EDX), M(&g_dsp.r.st[stack_reg])); MOV(16, R(EDX), M(&g_dsp.r.st[stack_reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(EDX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[stack_reg]))); MOV(16, R(EDX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[stack_reg])));
#endif #endif
dsp_reg_stack_pop(stack_reg); dsp_reg_stack_pop(stack_reg);
if (host_dreg != EDX) { if (host_dreg != EDX) {
@ -136,8 +136,8 @@ void DSPEmitter::dsp_reg_store_stack_imm(int stack_reg, u16 val)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.st[stack_reg]), Imm16(val)); MOV(16, M(&g_dsp.r.st[stack_reg]), Imm16(val));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, st[stack_reg])), Imm16(val)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, st[stack_reg])), Imm16(val));
#endif #endif
} }
@ -148,12 +148,12 @@ void DSPEmitter::dsp_op_write_reg(int reg, Gen::X64Reg host_sreg)
case DSP_REG_ACH0: case DSP_REG_ACH0:
case DSP_REG_ACH1: case DSP_REG_ACH1:
// sign extend from the bottom 8 bits. // sign extend from the bottom 8 bits.
MOVSX(16,8,host_sreg,R(host_sreg)); MOVSX(16, 8, host_sreg, R(host_sreg));
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[reg-DSP_REG_ACH0].h), R(host_sreg)); MOV(16, M(&g_dsp.r.ac[reg-DSP_REG_ACH0].h), R(host_sreg));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACH0].h)), R(host_sreg)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACH0].h)), R(host_sreg));
#endif #endif
break; break;
@ -171,8 +171,8 @@ void DSPEmitter::dsp_op_write_reg(int reg, Gen::X64Reg host_sreg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(regp), R(host_sreg)); MOV(16, M(regp), R(host_sreg));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,PtrOffset(regp,&g_dsp.r)), R(host_sreg)); MOV(16, MDisp(R11, PtrOffset(regp, &g_dsp.r)), R(host_sreg));
#endif #endif
break; break;
} }
@ -189,8 +189,8 @@ void DSPEmitter::dsp_op_write_reg_imm(int reg, u16 val)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ac[reg-DSP_REG_ACH0].h), Imm16((u16)(s16)(s8)(u8)val)); MOV(16, M(&g_dsp.r.ac[reg-DSP_REG_ACH0].h), Imm16((u16)(s16)(s8)(u8)val));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACH0].h)), Imm16((u16)(s16)(s8)(u8)val)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACH0].h)), Imm16((u16)(s16)(s8)(u8)val));
#endif #endif
break; break;
@ -208,8 +208,8 @@ void DSPEmitter::dsp_op_write_reg_imm(int reg, u16 val)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(regp), Imm16(val)); MOV(16, M(regp), Imm16(val));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,PtrOffset(regp,&g_dsp.r)), Imm16(val)); MOV(16, MDisp(R11, PtrOffset(regp, &g_dsp.r)), Imm16(val));
#endif #endif
break; break;
} }
@ -226,8 +226,8 @@ void DSPEmitter::dsp_conditional_extend_accum(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(EAX), M(&g_dsp.r.sr)); MOV(16, R(EAX), M(&g_dsp.r.sr));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(EAX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, sr))); MOV(16, R(EAX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)));
#endif #endif
TEST(16, R(EAX), Imm16(SR_40_MODE_BIT)); TEST(16, R(EAX), Imm16(SR_40_MODE_BIT));
FixupBranch not_40bit = J_CC(CC_Z); FixupBranch not_40bit = J_CC(CC_Z);
@ -238,19 +238,19 @@ void DSPEmitter::dsp_conditional_extend_accum(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOVSX(32, 16, EAX, M(&g_dsp.r.ac[reg-DSP_REG_ACM0].m)); MOVSX(32, 16, EAX, M(&g_dsp.r.ac[reg-DSP_REG_ACM0].m));
#else #else
MOVSX(64, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].m))); MOVSX(64, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].m)));
#endif #endif
SHR(32,R(EAX),Imm8(16)); SHR(32, R(EAX), Imm8(16));
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16,M(&g_dsp.r.ac[reg - DSP_REG_ACM0].h), MOV(16, M(&g_dsp.r.ac[reg - DSP_REG_ACM0].h),
R(EAX)); R(EAX));
MOV(16,M(&g_dsp.r.ac[reg - DSP_REG_ACM0].l), MOV(16, M(&g_dsp.r.ac[reg - DSP_REG_ACM0].l),
Imm16(0)); Imm16(0));
#else #else
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].h)), R(EAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].h)), R(EAX));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].l)), Imm16(0)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].l)), Imm16(0));
#endif #endif
//} //}
SetJumpTarget(not_40bit); SetJumpTarget(not_40bit);
@ -268,8 +268,8 @@ void DSPEmitter::dsp_conditional_extend_accum_imm(int reg, u16 val)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(EAX), M(&g_dsp.r.sr)); MOV(16, R(EAX), M(&g_dsp.r.sr));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(EAX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, sr))); MOV(16, R(EAX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)));
#endif #endif
TEST(16, R(EAX), Imm16(SR_40_MODE_BIT)); TEST(16, R(EAX), Imm16(SR_40_MODE_BIT));
FixupBranch not_40bit = J_CC(CC_Z); FixupBranch not_40bit = J_CC(CC_Z);
@ -279,14 +279,14 @@ void DSPEmitter::dsp_conditional_extend_accum_imm(int reg, u16 val)
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0; //g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16,M(&g_dsp.r.ac[reg - DSP_REG_ACM0].h), MOV(16, M(&g_dsp.r.ac[reg - DSP_REG_ACM0].h),
Imm16((val & 0x8000)?0xffff:0x0000)); Imm16((val & 0x8000)?0xffff:0x0000));
MOV(16,M(&g_dsp.r.ac[reg - DSP_REG_ACM0].l), MOV(16, M(&g_dsp.r.ac[reg - DSP_REG_ACM0].l),
Imm16(0)); Imm16(0));
#else #else
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].h)), MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].h)),
Imm16((val & 0x8000)?0xffff:0x0000)); Imm16((val & 0x8000)?0xffff:0x0000));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].l)), MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[reg-DSP_REG_ACM0].l)),
Imm16(0)); Imm16(0));
#endif #endif
//} //}
@ -310,8 +310,8 @@ void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, R(host_dreg), M(regp)); MOV(16, R(host_dreg), M(regp));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(host_dreg), MDisp(R11,PtrOffset(regp,&g_dsp.r))); MOV(16, R(host_dreg), MDisp(R11, PtrOffset(regp, &g_dsp.r)));
#endif #endif
} }
} }
@ -427,8 +427,8 @@ void DSPEmitter::setCompileSR(u16 bit) {
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
OR(16, M(&g_dsp.r.sr), Imm16(bit)); OR(16, M(&g_dsp.r.sr), Imm16(bit));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
OR(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, sr)), Imm16(bit)); OR(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(bit));
#endif #endif
compileSR |= bit; compileSR |= bit;
@ -440,8 +440,8 @@ void DSPEmitter::clrCompileSR(u16 bit) {
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
AND(16, M(&g_dsp.r.sr), Imm16(~bit)); AND(16, M(&g_dsp.r.sr), Imm16(~bit));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
AND(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, sr)), Imm16(~bit)); AND(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, sr)), Imm16(~bit));
#endif #endif
compileSR &= ~bit; compileSR &= ~bit;

24
Source/Core/DSPCore/Src/Jit/DSPJitMultiplier.cpp
View File

@ -156,7 +156,7 @@ void DSPEmitter::clrp(const UDSPInstruction opc)
{ {
#ifdef _M_X64 #ifdef _M_X64
// g_dsp.r[DSP_REG_PRODL] = 0x0000; // g_dsp.r[DSP_REG_PRODL] = 0x0000;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.l)), Imm16(0x0000)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.l)), Imm16(0x0000));
// g_dsp.r[DSP_REG_PRODM] = 0xfff0; // g_dsp.r[DSP_REG_PRODM] = 0xfff0;
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.m)), Imm16(0xfff0)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.m)), Imm16(0xfff0));
@ -317,7 +317,7 @@ void DSPEmitter::mulaxh(const UDSPInstruction opc)
{ {
#ifdef _M_X64 #ifdef _M_X64
// s64 prod = dsp_multiply(dsp_get_ax_h(0), dsp_get_ax_h(0)); // s64 prod = dsp_multiply(dsp_get_ax_h(0), dsp_get_ax_h(0));
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[0].h))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[0].h)));
MOV(64, R(RDI), R(RSI)); MOV(64, R(RDI), R(RSI));
multiply(); multiply();
@ -340,7 +340,7 @@ void DSPEmitter::mul(const UDSPInstruction opc)
u8 sreg = (opc >> 11) & 0x1; u8 sreg = (opc >> 11) & 0x1;
// u16 axl = dsp_get_ax_l(sreg); // u16 axl = dsp_get_ax_l(sreg);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l)));
// u16 axh = dsp_get_ax_h(sreg); // u16 axh = dsp_get_ax_h(sreg);
MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].h))); MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].h)));
@ -464,7 +464,7 @@ void DSPEmitter::mulx(const UDSPInstruction opc)
u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2); u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2);
u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2); u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); // u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0);
MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp,&g_dsp.r))); MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp,&g_dsp.r)));
// u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); // u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1);
@ -611,7 +611,7 @@ void DSPEmitter::mulc(const UDSPInstruction opc)
u8 sreg = (opc >> 12) & 0x1; u8 sreg = (opc >> 12) & 0x1;
// u16 accm = dsp_get_acc_m(sreg); // u16 accm = dsp_get_acc_m(sreg);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, ESI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVSX(64, 16, ESI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
// u16 axh = dsp_get_ax_h(treg); // u16 axh = dsp_get_ax_h(treg);
MOVSX(64, 16, EDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[treg].h))); MOVSX(64, 16, EDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[treg].h)));
@ -720,7 +720,7 @@ void DSPEmitter::mulcmvz(const UDSPInstruction opc)
u8 treg = (opc >> 11) & 0x1; u8 treg = (opc >> 11) & 0x1;
u8 sreg = (opc >> 12) & 0x1; u8 sreg = (opc >> 12) & 0x1;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// s64 acc = dsp_get_long_prod_round_prodl(); // s64 acc = dsp_get_long_prod_round_prodl();
get_long_prod_round_prodl(); get_long_prod_round_prodl();
PUSH(64, R(RAX)); PUSH(64, R(RAX));
@ -760,7 +760,7 @@ void DSPEmitter::maddx(const UDSPInstruction opc)
u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2); u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2);
u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2); u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); // u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0);
MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp, &g_dsp.r))); MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
// u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); // u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1);
@ -787,7 +787,7 @@ void DSPEmitter::msubx(const UDSPInstruction opc)
u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2); u16 *sregp = reg_ptr(DSP_REG_AXL0 + sreg*2);
u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2); u16 *tregp = reg_ptr(DSP_REG_AXL1 + treg*2);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); // u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0);
MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp, &g_dsp.r))); MOVSX(64, 16, RSI, MDisp(R11, PtrOffset(sregp, &g_dsp.r)));
// u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); // u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1);
@ -812,7 +812,7 @@ void DSPEmitter::maddc(const UDSPInstruction opc)
u8 treg = (opc >> 8) & 0x1; u8 treg = (opc >> 8) & 0x1;
u8 sreg = (opc >> 9) & 0x1; u8 sreg = (opc >> 9) & 0x1;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// u16 accm = dsp_get_acc_m(sreg); // u16 accm = dsp_get_acc_m(sreg);
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
// u16 axh = dsp_get_ax_h(treg); // u16 axh = dsp_get_ax_h(treg);
@ -838,7 +838,7 @@ void DSPEmitter::msubc(const UDSPInstruction opc)
u8 sreg = (opc >> 9) & 0x1; u8 sreg = (opc >> 9) & 0x1;
// u16 accm = dsp_get_acc_m(sreg); // u16 accm = dsp_get_acc_m(sreg);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[sreg].m)));
// u16 axh = dsp_get_ax_h(treg); // u16 axh = dsp_get_ax_h(treg);
MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[treg].h))); MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[treg].h)));
@ -861,7 +861,7 @@ void DSPEmitter::madd(const UDSPInstruction opc)
#ifdef _M_X64 #ifdef _M_X64
u8 sreg = (opc >> 8) & 0x1; u8 sreg = (opc >> 8) & 0x1;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
// u16 axl = dsp_get_ax_l(sreg); // u16 axl = dsp_get_ax_l(sreg);
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l)));
// u16 axh = dsp_get_ax_h(sreg); // u16 axh = dsp_get_ax_h(sreg);
@ -886,7 +886,7 @@ void DSPEmitter::msub(const UDSPInstruction opc)
u8 sreg = (opc >> 8) & 0x1; u8 sreg = (opc >> 8) & 0x1;
// //
// u16 axl = dsp_get_ax_l(sreg); // u16 axl = dsp_get_ax_l(sreg);
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l))); MOVSX(64, 16, RSI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].l)));
// u16 axh = dsp_get_ax_h(sreg); // u16 axh = dsp_get_ax_h(sreg);
MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].h))); MOVSX(64, 16, RDI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[sreg].h)));

154
Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
View File

@ -44,7 +44,7 @@ void DSPEmitter::ToMask(X64Reg value_reg)
MOV(16, R(CX), R(value_reg)); MOV(16, R(CX), R(value_reg));
SHR(16, R(CX), Imm8(1)); SHR(16, R(CX), Imm8(1));
OR(16, R(value_reg), R(CX)); OR(16, R(value_reg), R(CX));
MOVZX(32,16,value_reg, R(value_reg)); MOVZX(32, 16, value_reg, R(value_reg));
#else #else
BSR(16, CX, R(value_reg)); BSR(16, CX, R(value_reg));
FixupBranch undef = J_CC(CC_Z); //CX is written, but undefined FixupBranch undef = J_CC(CC_Z); //CX is written, but undefined
@ -80,23 +80,23 @@ void DSPEmitter::increment_addr_reg(int reg)
MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg])); MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg]));
MOV(16, R(DX), M(&g_dsp.r.wr[reg])); MOV(16, R(DX), M(&g_dsp.r.wr[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(32, 16, EAX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
MOV(16, R(DX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, wr[reg]))); MOV(16, R(DX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
#endif #endif
MOV(32,R(EDI), R(EAX)); MOV(32, R(EDI), R(EAX));
ADD(32,R(EAX), Imm32(1)); ADD(32, R(EAX), Imm32(1));
XOR(32,R(EDI), R(EAX)); XOR(32, R(EDI), R(EAX));
MOVZX(32, 16, ESI, R(DX)); MOVZX(32, 16, ESI, R(DX));
SHL(32,R(ESI), Imm8(1)); SHL(32, R(ESI), Imm8(1));
OR(32,R(ESI), Imm32(3)); OR(32, R(ESI), Imm32(3));
CMP(32,R(EDI), R(ESI)); CMP(32, R(EDI), R(ESI));
FixupBranch nowrap = J_CC(CC_B); FixupBranch nowrap = J_CC(CC_B);
SUB(16,R(AX), R(DX)); SUB(16, R(AX), R(DX));
SUB(16,R(AX), Imm16(1)); SUB(16, R(AX), Imm16(1));
SetJumpTarget(nowrap); SetJumpTarget(nowrap);
@ -104,8 +104,8 @@ void DSPEmitter::increment_addr_reg(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ar[reg]), R(AX)); MOV(16, M(&g_dsp.r.ar[reg]), R(AX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg])), R(AX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(AX));
#endif #endif
} }
@ -129,9 +129,9 @@ void DSPEmitter::decrement_addr_reg(int reg)
MOV(16, R(AX), M(&g_dsp.r.ar[reg])); MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg])); MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(AX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
MOVZX(32, 16, EDX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, wr[reg]))); MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
#endif #endif
// ToMask(WR0), calculating it into EDI // ToMask(WR0), calculating it into EDI
@ -151,8 +151,8 @@ void DSPEmitter::decrement_addr_reg(int reg)
SUB(32, R(EDI), R(EDX)); SUB(32, R(EDI), R(EDX));
CMP(32, R(ECX), R(EDI)); CMP(32, R(ECX), R(EDI));
FixupBranch out1 = J_CC(CC_GE); FixupBranch out1 = J_CC(CC_GE);
ADD(16,R(AX),R(DX)); ADD(16, R(AX), R(DX));
ADD(16,R(AX),Imm16(1)); ADD(16, R(AX), Imm16(1));
SetJumpTarget(out1); SetJumpTarget(out1);
@ -160,8 +160,8 @@ void DSPEmitter::decrement_addr_reg(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ar[reg]), R(AX)); MOV(16, M(&g_dsp.r.ar[reg]), R(AX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg])), R(AX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(AX));
#endif #endif
} }
@ -193,10 +193,10 @@ void DSPEmitter::increase_addr_reg(int reg)
MOV(16, R(AX), M(&g_dsp.r.ar[reg])); MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg])); MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(SI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ix[reg]))); MOV(16, R(SI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
MOV(16, R(AX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
MOVZX(32, 16, EDX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, wr[reg]))); MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
#endif #endif
// ToMask(WR0), calculating it into EDI // ToMask(WR0), calculating it into EDI
@ -208,7 +208,7 @@ void DSPEmitter::increase_addr_reg(int reg)
MOV(16, R(CX), R(AX)); MOV(16, R(CX), R(AX));
ADD(16, R(AX), R(SI)); ADD(16, R(AX), R(SI));
TEST(16,R(SI), Imm16(0x8000)); TEST(16, R(SI), Imm16(0x8000));
FixupBranch negative = J_CC(CC_NZ); FixupBranch negative = J_CC(CC_NZ);
//(ar&m) + (ix&m) -(int)m-1 //(ar&m) + (ix&m) -(int)m-1
@ -220,8 +220,8 @@ void DSPEmitter::increase_addr_reg(int reg)
CMP(32, R(ECX), Imm32(0)); CMP(32, R(ECX), Imm32(0));
FixupBranch out1 = J_CC(CC_L); FixupBranch out1 = J_CC(CC_L);
SUB(16,R(AX),R(DX)); SUB(16, R(AX), R(DX));
SUB(16,R(AX),Imm16(1)); SUB(16, R(AX), Imm16(1));
FixupBranch out2 = J(); FixupBranch out2 = J();
SetJumpTarget(negative); SetJumpTarget(negative);
@ -236,8 +236,8 @@ void DSPEmitter::increase_addr_reg(int reg)
SUB(32, R(EDI), R(EDX)); SUB(32, R(EDI), R(EDX));
CMP(32, R(ECX), R(EDI)); CMP(32, R(ECX), R(EDI));
FixupBranch out3 = J_CC(CC_GE); FixupBranch out3 = J_CC(CC_GE);
ADD(16,R(AX),R(DX)); ADD(16, R(AX), R(DX));
ADD(16,R(AX),Imm16(1)); ADD(16, R(AX), Imm16(1));
SetJumpTarget(out1); SetJumpTarget(out1);
SetJumpTarget(out2); SetJumpTarget(out2);
@ -247,8 +247,8 @@ void DSPEmitter::increase_addr_reg(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ar[reg]), R(EAX)); MOV(16, M(&g_dsp.r.ar[reg]), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX));
#endif #endif
} }
@ -280,10 +280,10 @@ void DSPEmitter::decrease_addr_reg(int reg)
MOV(16, R(AX), M(&g_dsp.r.ar[reg])); MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg])); MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, R(SI), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ix[reg]))); MOV(16, R(SI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
MOV(16, R(AX), MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg]))); MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
MOVZX(32, 16, EDX, MDisp(R11,STRUCT_OFFSET(g_dsp.r, wr[reg]))); MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
#endif #endif
// ToMask(WR0), calculating it into EDI // ToMask(WR0), calculating it into EDI
@ -295,7 +295,7 @@ void DSPEmitter::decrease_addr_reg(int reg)
MOV(16, R(CX), R(AX)); MOV(16, R(CX), R(AX));
SUB(16, R(AX), R(SI)); SUB(16, R(AX), R(SI));
CMP(16,R(SI), Imm16(0x8000)); CMP(16, R(SI), Imm16(0x8000));
FixupBranch negative = J_CC(CC_BE); FixupBranch negative = J_CC(CC_BE);
//(ar&m) + (ix&m) //(ar&m) + (ix&m)
@ -305,8 +305,8 @@ void DSPEmitter::decrease_addr_reg(int reg)
CMP(32, R(ECX), Imm32(0)); CMP(32, R(ECX), Imm32(0));
FixupBranch out1 = J_CC(CC_L); FixupBranch out1 = J_CC(CC_L);
SUB(16,R(AX),R(DX)); SUB(16, R(AX), R(DX));
SUB(16,R(AX),Imm16(1)); SUB(16, R(AX), Imm16(1));
FixupBranch out2 = J(); FixupBranch out2 = J();
SetJumpTarget(negative); SetJumpTarget(negative);
@ -320,8 +320,8 @@ void DSPEmitter::decrease_addr_reg(int reg)
SUB(32, R(EDI), R(EDX)); SUB(32, R(EDI), R(EDX));
CMP(32, R(ECX), R(EDI)); CMP(32, R(ECX), R(EDI));
FixupBranch out3 = J_CC(CC_GE); FixupBranch out3 = J_CC(CC_GE);
ADD(16,R(AX),R(DX)); ADD(16, R(AX), R(DX));
ADD(16,R(AX),Imm16(1)); ADD(16, R(AX), Imm16(1));
SetJumpTarget(out1); SetJumpTarget(out1);
SetJumpTarget(out2); SetJumpTarget(out2);
@ -331,8 +331,8 @@ void DSPEmitter::decrease_addr_reg(int reg)
#ifdef _M_IX86 // All32 #ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r.ar[reg]), R(EAX)); MOV(16, M(&g_dsp.r.ar[reg]), R(EAX));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX));
#endif #endif
} }
@ -359,7 +359,9 @@ void DSPEmitter::dmem_write()
// else if (saddr == 0xf) // else if (saddr == 0xf)
SetJumpTarget(ifx); SetJumpTarget(ifx);
// Does it mean gdsp_ifx_write needs u32 rather than u16? // Does it mean gdsp_ifx_write needs u32 rather than u16?
SaveDSPRegs();
ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX); ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX);
LoadDSPRegs();
SetJumpTarget(end); SetJumpTarget(end);
} }
@ -373,13 +375,15 @@ void DSPEmitter::dmem_write_imm(u16 address)
MOV(16, M(&g_dsp.dram[address & DSP_DRAM_MASK]), R(ECX)); MOV(16, M(&g_dsp.dram[address & DSP_DRAM_MASK]), R(ECX));
#else #else
MOV(64, R(RDX), ImmPtr(g_dsp.dram)); MOV(64, R(RDX), ImmPtr(g_dsp.dram));
MOV(16, MDisp(RDX,(address & DSP_DRAM_MASK)*2), R(ECX)); MOV(16, MDisp(RDX, (address & DSP_DRAM_MASK)*2), R(ECX));
#endif #endif
break; break;
case 0xf: // Fxxx HW regs case 0xf: // Fxxx HW regs
MOV(16, R(EAX), Imm16(address)); MOV(16, R(EAX), Imm16(address));
SaveDSPRegs();
ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX); ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX);
LoadDSPRegs();
break; break;
default: // Unmapped/non-existing memory default: // Unmapped/non-existing memory
@ -416,7 +420,7 @@ void DSPEmitter::imem_read()
#else #else
MOV(32, R(ESI), ImmPtr(g_dsp.irom)); MOV(32, R(ESI), ImmPtr(g_dsp.irom));
#endif #endif
MOV(16, R(EAX), MComplex(ESI,ECX,2,0)); MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
SetJumpTarget(end); SetJumpTarget(end);
} }
@ -455,14 +459,15 @@ void DSPEmitter::dmem_read()
AND(32, R(ECX), Imm32(DSP_COEF_MASK)); AND(32, R(ECX), Imm32(DSP_COEF_MASK));
MOV(32, R(ESI), ImmPtr(g_dsp.coef)); MOV(32, R(ESI), ImmPtr(g_dsp.coef));
#endif #endif
MOV(16, R(EAX), MComplex(ESI,ECX,2,0)); MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
FixupBranch end2 = J(); FixupBranch end2 = J();
SetJumpTarget(ifx); SetJumpTarget(ifx);
// else if (saddr == 0xf) // else if (saddr == 0xf)
// return gdsp_ifx_read(addr); // return gdsp_ifx_read(addr);
SaveDSPRegs();
ABI_CallFunctionR((void *)gdsp_ifx_read, ECX); ABI_CallFunctionR((void *)gdsp_ifx_read, ECX);
LoadDSPRegs();
SetJumpTarget(end); SetJumpTarget(end);
SetJumpTarget(end2); SetJumpTarget(end2);
} }
@ -476,7 +481,7 @@ void DSPEmitter::dmem_read_imm(u16 address)
MOV(16, R(EAX), M(&g_dsp.dram[address & DSP_DRAM_MASK])); MOV(16, R(EAX), M(&g_dsp.dram[address & DSP_DRAM_MASK]));
#else #else
MOV(64, R(RDX), ImmPtr(g_dsp.dram)); MOV(64, R(RDX), ImmPtr(g_dsp.dram));
MOV(16, R(EAX), MDisp(RDX,(address & DSP_DRAM_MASK)*2)); MOV(16, R(EAX), MDisp(RDX, (address & DSP_DRAM_MASK)*2));
#endif #endif
break; break;
@ -485,12 +490,14 @@ void DSPEmitter::dmem_read_imm(u16 address)
MOV(16, R(EAX), Imm16(g_dsp.coef[address & DSP_COEF_MASK])); MOV(16, R(EAX), Imm16(g_dsp.coef[address & DSP_COEF_MASK]));
#else #else
MOV(64, R(RDX), ImmPtr(g_dsp.coef)); MOV(64, R(RDX), ImmPtr(g_dsp.coef));
MOV(16, R(EAX), MDisp(RDX,(address & DSP_COEF_MASK)*2)); MOV(16, R(EAX), MDisp(RDX, (address & DSP_COEF_MASK)*2));
#endif #endif
break; break;
case 0xf: // Fxxx HW regs case 0xf: // Fxxx HW regs
SaveDSPRegs();
ABI_CallFunctionC16((void *)gdsp_ifx_read, address); ABI_CallFunctionC16((void *)gdsp_ifx_read, address);
LoadDSPRegs();
break; break;
default: // Unmapped/non-existing memory default: // Unmapped/non-existing memory
@ -504,24 +511,24 @@ void DSPEmitter::get_long_prod(X64Reg long_prod)
{ {
#ifdef _M_X64 #ifdef _M_X64
#if 0 #if 0
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
//s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH]; //s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH];
MOVSX(64, 8, long_prod, MDisp(R11,STRUCT_OFFSET(g_dsp.r, prod.h))); MOVSX(64, 8, long_prod, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.h)));
//val <<= 32; //val <<= 32;
SHL(64, R(long_prod), Imm8(16)); SHL(64, R(long_prod), Imm8(16));
//s64 low_prod = g_dsp.r[DSP_REG_PRODM]; //s64 low_prod = g_dsp.r[DSP_REG_PRODM];
OR(16, R(long_prod), MDisp(R11,STRUCT_OFFSET(g_dsp.r, prod.m))); OR(16, R(long_prod), MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.m)));
//low_prod += g_dsp.r[DSP_REG_PRODM2]; //low_prod += g_dsp.r[DSP_REG_PRODM2];
ADD(16, R(long_prod), MDisp(R11,STRUCT_OFFSET(g_dsp.r, prod.m2))); ADD(16, R(long_prod), MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.m2)));
//low_prod <<= 16; //low_prod <<= 16;
SHL(64, R(long_prod), Imm8(16)); SHL(64, R(long_prod), Imm8(16));
//low_prod |= g_dsp.r[DSP_REG_PRODL]; //low_prod |= g_dsp.r[DSP_REG_PRODL];
OR(16, R(long_prod), MDisp(R11,STRUCT_OFFSET(g_dsp.r, prod.l))); OR(16, R(long_prod), MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.l)));
//return val; //return val;
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
//s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH]; //s64 val = (s8)(u8)g_dsp.r[DSP_REG_PRODH];
MOV(64, R(long_prod), MDisp(R11,STRUCT_OFFSET(g_dsp.r, prod.val))); MOV(64, R(long_prod), MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.val)));
MOV(64, R(R11), R(long_prod)); MOV(64, R(R11), R(long_prod));
SHL(64, R(long_prod), Imm8(64-40));//sign extend SHL(64, R(long_prod), Imm8(64-40));//sign extend
SAR(64, R(long_prod), Imm8(64-40)); SAR(64, R(long_prod), Imm8(64-40));
@ -567,7 +574,7 @@ void DSPEmitter::set_long_prod()
#ifdef _M_X64 #ifdef _M_X64
#if 0 #if 0
// g_dsp.r[DSP_REG_PRODL] = (u16)val; // g_dsp.r[DSP_REG_PRODL] = (u16)val;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.l)), R(AX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, prod.l)), R(AX));
// val >>= 16; // val >>= 16;
SAR(64, R(RAX), Imm8(16)); SAR(64, R(RAX), Imm8(16));
@ -618,7 +625,7 @@ void DSPEmitter::get_long_acc(int _reg, X64Reg acc)
#ifdef _M_X64 #ifdef _M_X64
#if 0 #if 0
// s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32; // s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 8, acc, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].h))); MOVSX(64, 8, acc, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].h)));
SHL(64, R(acc), Imm8(16)); SHL(64, R(acc), Imm8(16));
// u32 mid_low = ((u32)g_dsp.r[DSP_REG_ACM0 + reg] << 16) | g_dsp.r[DSP_REG_ACL0 + reg]; // u32 mid_low = ((u32)g_dsp.r[DSP_REG_ACM0 + reg] << 16) | g_dsp.r[DSP_REG_ACL0 + reg];
@ -628,7 +635,7 @@ void DSPEmitter::get_long_acc(int _reg, X64Reg acc)
// return high | mid_low; // return high | mid_low;
#else #else
// s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32; // s64 high = (s64)(s8)g_dsp.r[DSP_REG_ACH0 + reg] << 32;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(64, R(acc), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].val))); MOV(64, R(acc), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].val)));
SHL(64, R(acc), Imm8(64-40));//sign extend SHL(64, R(acc), Imm8(64-40));//sign extend
SAR(64, R(acc), Imm8(64-40)); SAR(64, R(acc), Imm8(64-40));
@ -643,7 +650,7 @@ void DSPEmitter::set_long_acc(int _reg, X64Reg acc)
#ifdef _M_X64 #ifdef _M_X64
#if 0 #if 0
// g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val; // g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].l)), R(acc)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].l)), R(acc));
// val >>= 16; // val >>= 16;
SHR(64, R(acc), Imm8(16)); SHR(64, R(acc), Imm8(16));
@ -658,7 +665,7 @@ void DSPEmitter::set_long_acc(int _reg, X64Reg acc)
SHL(64, R(acc), Imm8(64-40));//sign extend SHL(64, R(acc), Imm8(64-40));//sign extend
SAR(64, R(acc), Imm8(64-40)); SAR(64, R(acc), Imm8(64-40));
// g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val; // g_dsp.r[DSP_REG_ACL0 + _reg] = (u16)val;
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(64, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].val)), R(acc)); MOV(64, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].val)), R(acc));
#endif #endif
#endif #endif
@ -669,7 +676,7 @@ void DSPEmitter::get_acc_m(int _reg, X64Reg acm)
{ {
// return g_dsp.r[DSP_REG_ACM0 + _reg]; // return g_dsp.r[DSP_REG_ACM0 + _reg];
#ifdef _M_X64 #ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, acm, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].m))); MOVSX(64, 16, acm, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].m)));
#endif #endif
} }
@ -679,7 +686,7 @@ void DSPEmitter::set_acc_m(int _reg)
{ {
// return g_dsp.r[DSP_REG_ACM0 + _reg]; // return g_dsp.r[DSP_REG_ACM0 + _reg];
#ifdef _M_X64 #ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].m)), R(RAX)); MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ac[_reg].m)), R(RAX));
#endif #endif
} }
@ -690,12 +697,12 @@ void DSPEmitter::get_long_acx(int _reg, X64Reg acx)
// return ((u32)g_dsp.r[DSP_REG_AXH0 + _reg] << 16) | g_dsp.r[DSP_REG_AXL0 + _reg]; // return ((u32)g_dsp.r[DSP_REG_AXH0 + _reg] << 16) | g_dsp.r[DSP_REG_AXL0 + _reg];
#ifdef _M_X64 #ifdef _M_X64
#if 0 #if 0
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, acx, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].h))); MOVSX(64, 16, acx, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].h)));
SHL(64, R(acx), Imm8(16)); SHL(64, R(acx), Imm8(16));
OR(16, R(acx), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].l))); OR(16, R(acx), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].l)));
#else #else
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 32, acx, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].val))); MOVSX(64, 32, acx, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].val)));
#endif #endif
#endif #endif
@ -706,7 +713,7 @@ void DSPEmitter::get_ax_l(int _reg, X64Reg axl)
{ {
// return (s16)g_dsp.r[DSP_REG_AXL0 + _reg]; // return (s16)g_dsp.r[DSP_REG_AXL0 + _reg];
#ifdef _M_X64 #ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, axl, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].l))); MOVSX(64, 16, axl, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].l)));
#endif #endif
} }
@ -716,7 +723,20 @@ void DSPEmitter::get_ax_h(int _reg, X64Reg axh)
{ {
// return (s16)g_dsp.r[DSP_REG_AXH0 + _reg]; // return (s16)g_dsp.r[DSP_REG_AXH0 + _reg];
#ifdef _M_X64 #ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r)); // MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVSX(64, 16, axh, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].h))); MOVSX(64, 16, axh, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ax[_reg].h)));
#endif #endif
} }
void DSPEmitter::LoadDSPRegs()
{
#ifdef _M_X64
MOV(64, R(R11), ImmPtr(&g_dsp.r));
#endif
// Load DSP register state here...
}
void DSPEmitter::SaveDSPRegs()
{
// Save DSP register state here...
}