Interpreter: support non-IEEE mode emulation
v2: fix fxsave on visual studio, thx @ rodolfo for this patch
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@ -43,6 +43,9 @@ struct CPUInfo
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bool bAVX;
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bool bFMA;
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bool bAES;
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// FXSAVE/FXRSTOR
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bool bFXSR;
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bool bDAZ;
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bool bLAHFSAHF64;
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bool bLongMode;
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@ -36,7 +36,7 @@ namespace FPURoundMode
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void SetPrecisionMode(u32 mode);
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void SetSIMDMode(u32 mode);
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void SetSIMDMode(u32 roundingMode, u32 nonIEEEMode);
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/*
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* There are two different flavors of float to int conversion:
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@ -26,7 +26,7 @@ namespace FPURoundMode
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void SetPrecisionMode(u32 mode)
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{
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}
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void SetSIMDMode(u32 mode)
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void SetSIMDMode(u32 mode, u32 nonIEEEMode)
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{
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}
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void SaveSIMDState()
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@ -162,6 +162,28 @@ void CPUInfo::Detect()
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if ((cpu_id[2] >> 20) & 1) bSSE4_2 = true;
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if ((cpu_id[2] >> 25) & 1) bAES = true;
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if ((cpu_id[3] >> 24) & 1)
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{
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// We can use FXSAVE.
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bFXSR = true;
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GC_ALIGNED16(u8 fx_state[512]);
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memset(fx_state, 0, sizeof(fx_state));
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#ifdef _WIN32
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#ifdef _M_IX86
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_fxsave(fx_state);
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#elif defined (_M_X64)
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_fxsave64(fx_state);
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#endif
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#else
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__asm__("fxsave %0" : "=m" (fx_state));
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#endif
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// lowest byte of MXCSR_MASK
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if ((fx_state[0x1C] >> 6) & 1)
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bDAZ = true;
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}
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// AVX support requires 3 separate checks:
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// - Is the AVX bit set in CPUID?
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// - Is the XSAVE bit set in CPUID?
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@ -4,6 +4,7 @@
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#include "Common.h"
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#include "FPURoundMode.h"
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#include "CPUDetect.h"
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#ifndef _WIN32
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static const unsigned short FPU_ROUND_NEAR = 0 << 10;
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@ -14,8 +15,11 @@ static const unsigned short FPU_ROUND_MASK = 3 << 10;
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#include <xmmintrin.h>
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#endif
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const u32 MASKS = 0x1F80; // mask away the interrupts.
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// OR-mask for disabling FPU exceptions (bits 7-12 in the MXCSR register)
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const u32 EXCEPTION_MASK = 0x1F80;
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// Denormals-Are-Zero (non-IEEE mode: denormal inputs are set to +/- 0)
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const u32 DAZ = 0x40;
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// Flush-To-Zero (non-IEEE mode: denormal outputs are set to +/- 0)
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const u32 FTZ = 0x8000;
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namespace FPURoundMode
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@ -79,16 +83,28 @@ namespace FPURoundMode
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//but still - set any useful sse options here
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#endif
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}
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void SetSIMDMode(u32 mode)
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void SetSIMDMode(u32 roundingMode, u32 nonIEEEMode)
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{
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static const u32 ssetable[4] =
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// lookup table for FPSCR.RN-to-MXCSR.RC translation
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static const u32 roundingModeLUT[4] =
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{
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(0 << 13) | MASKS,
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(3 << 13) | MASKS,
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(2 << 13) | MASKS,
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(1 << 13) | MASKS,
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(0 << 13) | EXCEPTION_MASK, // nearest
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(3 << 13) | EXCEPTION_MASK, // -inf
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(2 << 13) | EXCEPTION_MASK, // +inf
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(1 << 13) | EXCEPTION_MASK, // zero
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};
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u32 csr = ssetable[mode];
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u32 csr = roundingModeLUT[roundingMode];
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static const u32 denormalLUT[2] =
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{
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FTZ, // flush-to-zero only
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FTZ | DAZ, // flush-to-zero and denormals-are-zero (may not be supported)
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};
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if (nonIEEEMode)
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{
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csr |= denormalLUT[cpu_info.bDAZ];
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}
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_mm_setcsr(csr);
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}
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@ -48,15 +48,8 @@ static void FPSCRtoFPUSettings(UReg_FPSCR fp)
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// Pokemon Colosseum does this. Gah.
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}
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// Also corresponding SSE rounding mode setting
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if (FPSCR.NI)
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{
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// Either one of these two breaks Beyond Good & Evil.
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// if (cpu_info.bSSSE3)
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// csr |= DAZ;
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// csr |= FTZ;
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}
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FPURoundMode::SetSIMDMode(FPSCR.RN);
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// Set SSE rounding mode and denormal handling
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FPURoundMode::SetSIMDMode(FPSCR.RN, FPSCR.NI);
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}
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void Interpreter::mtfsb0x(UGeckoInstruction _inst)
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