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Merge pull request #4708 from degasus/PIE 

Jit64: Use a temporary register for memory references.
This commit is contained in:
Markus Wick 2017-04-14 09:42:45 +02:00 committed by GitHub
parent 722aca0830 64ccf803bd
commit 45e4a048ea
5 changed files with 14 additions and 8 deletions
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2
Source/Core/Core/HW/CPU.cpp
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@ -183,7 +183,7 @@ State GetState()
return s_state; return s_state;
} }
const volatile State* GetStatePtr() const State* GetStatePtr()
{ {
return &s_state; return &s_state;
} }

2
Source/Core/Core/HW/CPU.h
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@ -57,7 +57,7 @@ State GetState();
// Direct State Access (Raw pointer for embedding into JIT Blocks) // Direct State Access (Raw pointer for embedding into JIT Blocks)
// Strictly read-only. A lock is required to change the value. // Strictly read-only. A lock is required to change the value.
const volatile State* GetStatePtr(); const State* GetStatePtr();
// Locks the CPU Thread (waiting for it to become idle). // Locks the CPU Thread (waiting for it to become idle).
// While this lock is held, the CPU Thread will not perform any action so it is safe to access // While this lock is held, the CPU Thread will not perform any action so it is safe to access

6
Source/Core/Core/PowerPC/Jit64/Jit.cpp
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@ -780,7 +780,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc
SetJumpTarget(extException); SetJumpTarget(extException);
TEST(32, PPCSTATE(msr), Imm32(0x0008000)); TEST(32, PPCSTATE(msr), Imm32(0x0008000));
FixupBranch noExtIntEnable = J_CC(CC_Z, true); FixupBranch noExtIntEnable = J_CC(CC_Z, true);
TEST(32, M(&ProcessorInterface::m_InterruptCause), MOV(64, R(RSCRATCH), ImmPtr(&ProcessorInterface::m_InterruptCause));
TEST(32, MatR(RSCRATCH),
Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN |
ProcessorInterface::INT_CAUSE_PE_FINISH)); ProcessorInterface::INT_CAUSE_PE_FINISH));
FixupBranch noCPInt = J_CC(CC_Z, true); FixupBranch noCPInt = J_CC(CC_Z, true);
@ -854,7 +855,8 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc
ABI_PushRegistersAndAdjustStack({}, 0); ABI_PushRegistersAndAdjustStack({}, 0);
ABI_CallFunction(PowerPC::CheckBreakPoints); ABI_CallFunction(PowerPC::CheckBreakPoints);
ABI_PopRegistersAndAdjustStack({}, 0); ABI_PopRegistersAndAdjustStack({}, 0);
TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr()));
TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
FixupBranch noBreakpoint = J_CC(CC_Z); FixupBranch noBreakpoint = J_CC(CC_Z);
WriteExit(ops[i].address); WriteExit(ops[i].address);

9
Source/Core/Core/PowerPC/Jit64/JitAsm.cpp
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@ -84,12 +84,14 @@ void Jit64AsmRoutineManager::Generate()
if (SConfig::GetInstance().bEnableDebugging) if (SConfig::GetInstance().bEnableDebugging)
{ {
TEST(32, M(CPU::GetStatePtr()), Imm32(static_cast<u32>(CPU::State::Stepping))); MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr()));
TEST(32, MatR(RSCRATCH), Imm32(static_cast<u32>(CPU::State::Stepping)));
FixupBranch notStepping = J_CC(CC_Z); FixupBranch notStepping = J_CC(CC_Z);
ABI_PushRegistersAndAdjustStack({}, 0); ABI_PushRegistersAndAdjustStack({}, 0);
ABI_CallFunction(PowerPC::CheckBreakPoints); ABI_CallFunction(PowerPC::CheckBreakPoints);
ABI_PopRegistersAndAdjustStack({}, 0); ABI_PopRegistersAndAdjustStack({}, 0);
TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr()));
TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
dbg_exit = J_CC(CC_NZ, true); dbg_exit = J_CC(CC_NZ, true);
SetJumpTarget(notStepping); SetJumpTarget(notStepping);
} }
@ -187,7 +189,8 @@ void Jit64AsmRoutineManager::Generate()
// Check the state pointer to see if we are exiting // Check the state pointer to see if we are exiting
// Gets checked on at the end of every slice // Gets checked on at the end of every slice
TEST(32, M(CPU::GetStatePtr()), Imm32(0xFFFFFFFF)); MOV(64, R(RSCRATCH), ImmPtr(CPU::GetStatePtr()));
TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
J_CC(CC_Z, outerLoop); J_CC(CC_Z, outerLoop);
// Landing pad for drec space // Landing pad for drec space

3
Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
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@ -410,7 +410,8 @@ void Jit64::mtmsr(UGeckoInstruction inst)
FixupBranch noExceptionsPending = J_CC(CC_Z); FixupBranch noExceptionsPending = J_CC(CC_Z);
// Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336) // Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336)
TEST(32, M(&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP)); MOV(64, R(RSCRATCH), ImmPtr(&ProcessorInterface::m_InterruptCause));
TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP));
FixupBranch cpInt = J_CC(CC_NZ); FixupBranch cpInt = J_CC(CC_NZ);
MOV(32, PPCSTATE(pc), Imm32(js.compilerPC + 4)); MOV(32, PPCSTATE(pc), Imm32(js.compilerPC + 4));