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Gekko: Convert UReg_FPSCR over to using Common::BitField

This commit is contained in:
Lioncash 2021-08-27 11:01:32 -04:00
parent 4ecdcc9d78
commit 4591246608
2 changed files with 57 additions and 59 deletions
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114
Source/Core/Core/PowerPC/Gekko.h
View File

@ -429,64 +429,62 @@ enum FPSCRExceptionFlag : u32
// Floating Point Status and Control Register // Floating Point Status and Control Register
union UReg_FPSCR union UReg_FPSCR
{ {
struct // Rounding mode (towards: nearest, zero, +inf, -inf)
{ BitField<0, 2, FPURoundMode::RoundMode> RN;
// Rounding mode (towards: nearest, zero, +inf, -inf) // Non-IEEE mode enable (aka flush-to-zero)
FPURoundMode::RoundMode RN : 2; BitField<2, 1, u32> NI;
// Non-IEEE mode enable (aka flush-to-zero) // Inexact exception enable
u32 NI : 1; BitField<3, 1, u32> XE;
// Inexact exception enable // IEEE division by zero exception enable
u32 XE : 1; BitField<4, 1, u32> ZE;
// IEEE division by zero exception enable // IEEE underflow exception enable
u32 ZE : 1; BitField<5, 1, u32> UE;
// IEEE underflow exception enable // IEEE overflow exception enable
u32 UE : 1; BitField<6, 1, u32> OE;
// IEEE overflow exception enable // Invalid operation exception enable
u32 OE : 1; BitField<7, 1, u32> VE;
// Invalid operation exception enable // Invalid operation exception for integer conversion (sticky)
u32 VE : 1; BitField<8, 1, u32> VXCVI;
// Invalid operation exception for integer conversion (sticky) // Invalid operation exception for square root (sticky)
u32 VXCVI : 1; BitField<9, 1, u32> VXSQRT;
// Invalid operation exception for square root (sticky) // Invalid operation exception for software request (sticky)
u32 VXSQRT : 1; BitField<10, 1, u32> VXSOFT;
// Invalid operation exception for software request (sticky) // reserved
u32 VXSOFT : 1; BitField<11, 1, u32> reserved;
// reserved // Floating point result flags (includes FPCC) (not sticky)
u32 : 1; // from more to less significand: class, <, >, =, ?
// Floating point result flags (includes FPCC) (not sticky) BitField<12, 5, u32> FPRF;
// from more to less significand: class, <, >, =, ? // Fraction inexact (not sticky)
u32 FPRF : 5; BitField<17, 1, u32> FI;
// Fraction inexact (not sticky) // Fraction rounded (not sticky)
u32 FI : 1; BitField<18, 1, u32> FR;
// Fraction rounded (not sticky) // Invalid operation exception for invalid comparison (sticky)
u32 FR : 1; BitField<19, 1, u32> VXVC;
// Invalid operation exception for invalid comparison (sticky) // Invalid operation exception for inf * 0 (sticky)
u32 VXVC : 1; BitField<20, 1, u32> VXIMZ;
// Invalid operation exception for inf * 0 (sticky) // Invalid operation exception for 0 / 0 (sticky)
u32 VXIMZ : 1; BitField<21, 1, u32> VXZDZ;
// Invalid operation exception for 0 / 0 (sticky) // Invalid operation exception for inf / inf (sticky)
u32 VXZDZ : 1; BitField<22, 1, u32> VXIDI;
// Invalid operation exception for inf / inf (sticky) // Invalid operation exception for inf - inf (sticky)
u32 VXIDI : 1; BitField<23, 1, u32> VXISI;
// Invalid operation exception for inf - inf (sticky) // Invalid operation exception for SNaN (sticky)
u32 VXISI : 1; BitField<24, 1, u32> VXSNAN;
// Invalid operation exception for SNaN (sticky) // Inexact exception (sticky)
u32 VXSNAN : 1; BitField<25, 1, u32> XX;
// Inexact exception (sticky) // Division by zero exception (sticky)
u32 XX : 1; BitField<26, 1, u32> ZX;
// Division by zero exception (sticky) // Underflow exception (sticky)
u32 ZX : 1; BitField<27, 1, u32> UX;
// Underflow exception (sticky) // Overflow exception (sticky)
u32 UX : 1; BitField<28, 1, u32> OX;
// Overflow exception (sticky) // Invalid operation exception summary (not sticky)
u32 OX : 1; BitField<29, 1, u32> VX;
// Invalid operation exception summary (not sticky) // Enabled exception summary (not sticky)
u32 VX : 1; BitField<30, 1, u32> FEX;
// Enabled exception summary (not sticky) // Exception summary (sticky)
u32 FEX : 1; BitField<31, 1, u32> FX;
// Exception summary (sticky)
u32 FX : 1;
};
u32 Hex = 0; u32 Hex = 0;
// The FPSCR's 20th bit (11th from a little endian perspective) // The FPSCR's 20th bit (11th from a little endian perspective)

2
Source/Core/Core/PowerPC/Interpreter/Interpreter_FloatingPoint.cpp
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@ -226,7 +226,7 @@ void Interpreter::fcmpu(UGeckoInstruction inst)
void Interpreter::fctiwx(UGeckoInstruction inst) void Interpreter::fctiwx(UGeckoInstruction inst)
{ {
ConvertToInteger(inst, static_cast<RoundingMode>(FPSCR.RN)); ConvertToInteger(inst, static_cast<RoundingMode>(FPSCR.RN.Value()));
} }
void Interpreter::fctiwzx(UGeckoInstruction inst) void Interpreter::fctiwzx(UGeckoInstruction inst)