DSPInterpreter: Rework overflow and carry handling
This commit is contained in:
Pokechu22
parent
7cd1b2c4d1
commit
4508ca6734
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@ -119,8 +119,7 @@ void Interpreter::cmp(const UDSPInstruction)
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const s64 acc1 = GetLongAcc(1);
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const s64 res = dsp_convert_long_acc(acc0 - acc1);
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UpdateSR64(res, isCarry2(acc0, res),
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isOverflow(acc0, -acc1, res)); // CF -> influence on ABS/0xa100
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UpdateSR64Sub(acc0, acc1, res);
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ZeroWriteBackLog();
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}
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@ -139,7 +138,7 @@ void Interpreter::cmpar(const UDSPInstruction opc)
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ax <<= 16;
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const s64 res = dsp_convert_long_acc(acc - ax);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -ax, res));
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UpdateSR64Sub(acc, ax, res);
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ZeroWriteBackLog();
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}
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@ -157,10 +156,11 @@ void Interpreter::cmpi(const UDSPInstruction opc)
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const s64 val = GetLongAcc(reg);
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// Immediate is considered to be at M level in the 40-bit accumulator.
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const s64 imm = (s64)(s16)state.FetchInstruction() << 16;
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s64 imm = static_cast<s16>(state.FetchInstruction());
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imm <<= 16;
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const s64 res = dsp_convert_long_acc(val - imm);
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UpdateSR64(res, isCarry2(val, res), isOverflow(val, -imm, res));
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UpdateSR64Sub(val, imm, res);
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}
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// CMPIS $acD, #I
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@ -175,11 +175,11 @@ void Interpreter::cmpis(const UDSPInstruction opc)
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const u8 areg = (opc >> 8) & 0x1;
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const s64 acc = GetLongAcc(areg);
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s64 val = (s8)opc;
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val <<= 16;
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const s64 res = dsp_convert_long_acc(acc - val);
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s64 imm = static_cast<s8>(opc);
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imm <<= 16;
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const s64 res = dsp_convert_long_acc(acc - imm);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -val, res));
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UpdateSR64Sub(acc, imm, res);
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}
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//----
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@ -401,13 +401,12 @@ void Interpreter::addr(const UDSPInstruction opc)
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}
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ax <<= 16;
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s64 res = acc + ax;
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const s64 res = acc + ax;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, ax, res));
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UpdateSR64Add(acc, ax, GetLongAcc(dreg));
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}
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// ADDAX $acD, $axS
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@ -422,13 +421,12 @@ void Interpreter::addax(const UDSPInstruction opc)
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const s64 acc = GetLongAcc(dreg);
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const s64 ax = GetLongACX(sreg);
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s64 res = acc + ax;
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const s64 res = acc + ax;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, ax, res));
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UpdateSR64Add(acc, ax, GetLongAcc(dreg));
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}
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// ADD $acD, $ac(1-D)
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@ -442,13 +440,12 @@ void Interpreter::add(const UDSPInstruction opc)
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const s64 acc0 = GetLongAcc(dreg);
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const s64 acc1 = GetLongAcc(1 - dreg);
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s64 res = acc0 + acc1;
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const s64 res = acc0 + acc1;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc0, res), isOverflow(acc0, acc1, res));
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UpdateSR64Add(acc0, acc1, GetLongAcc(dreg));
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}
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// ADDP $acD
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@ -462,13 +459,12 @@ void Interpreter::addp(const UDSPInstruction opc)
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const s64 acc = GetLongAcc(dreg);
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const s64 prod = GetLongProduct();
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s64 res = acc + prod;
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const s64 res = acc + prod;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, prod, res));
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UpdateSR64Add(acc, prod, GetLongAcc(dreg));
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}
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// ADDAXL $acD, $axS.l
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@ -484,15 +480,12 @@ void Interpreter::addaxl(const UDSPInstruction opc)
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const u64 acc = GetLongAcc(dreg);
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const u16 acx = static_cast<u16>(GetAXLow(sreg));
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u64 res = acc + acx;
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const u64 res = acc + acx;
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ZeroWriteBackLog();
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SetLongAcc(dreg, static_cast<s64>(res));
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res = GetLongAcc(dreg);
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UpdateSR64(static_cast<s64>(res), isCarry(acc, res),
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isOverflow(static_cast<s64>(acc), static_cast<s64>(acx), static_cast<s64>(res)));
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UpdateSR64Add(acc, acx, GetLongAcc(dreg));
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}
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// ADDI $amR, #I
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@ -509,11 +502,10 @@ void Interpreter::addi(const UDSPInstruction opc)
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const s64 acc = GetLongAcc(areg);
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s64 imm = static_cast<s16>(state.FetchInstruction());
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imm <<= 16;
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s64 res = acc + imm;
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const s64 res = acc + imm;
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SetLongAcc(areg, res);
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res = GetLongAcc(areg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, imm, res));
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UpdateSR64Add(acc, imm, GetLongAcc(areg));
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}
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// ADDIS $acD, #I
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@ -526,13 +518,12 @@ void Interpreter::addis(const UDSPInstruction opc)
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const u8 dreg = (opc >> 8) & 0x1;
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const s64 acc = GetLongAcc(dreg);
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s64 imm = static_cast<s8>(static_cast<u8>(opc));
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s64 imm = static_cast<s8>(opc);
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imm <<= 16;
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s64 res = acc + imm;
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const s64 res = acc + imm;
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, imm, res));
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UpdateSR64Add(acc, imm, GetLongAcc(dreg));
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}
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// INCM $acsD
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@ -546,13 +537,12 @@ void Interpreter::incm(const UDSPInstruction opc)
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const s64 sub = 0x10000;
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const s64 acc = GetLongAcc(dreg);
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s64 res = acc + sub;
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const s64 res = acc + sub;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, sub, res));
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UpdateSR64Add(acc, sub, GetLongAcc(dreg));
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}
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// INC $acD
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@ -565,13 +555,12 @@ void Interpreter::inc(const UDSPInstruction opc)
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const u8 dreg = (opc >> 8) & 0x1;
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const s64 acc = GetLongAcc(dreg);
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s64 res = acc + 1;
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const s64 res = acc + 1;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(acc, res), isOverflow(acc, 1, res));
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UpdateSR64Add(acc, 1, GetLongAcc(dreg));
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}
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//----
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@ -606,13 +595,12 @@ void Interpreter::subr(const UDSPInstruction opc)
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}
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ax <<= 16;
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s64 res = acc - ax;
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const s64 res = acc - ax;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -ax, res));
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UpdateSR64Sub(acc, ax, GetLongAcc(dreg));
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}
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// SUBAX $acD, $axS
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@ -627,13 +615,12 @@ void Interpreter::subax(const UDSPInstruction opc)
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const s64 acc = GetLongAcc(dreg);
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const s64 acx = GetLongACX(sreg);
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s64 res = acc - acx;
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const s64 res = acc - acx;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -acx, res));
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UpdateSR64Sub(acc, acx, GetLongAcc(dreg));
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}
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// SUB $acD, $ac(1-D)
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@ -647,13 +634,12 @@ void Interpreter::sub(const UDSPInstruction opc)
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const s64 acc1 = GetLongAcc(dreg);
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const s64 acc2 = GetLongAcc(1 - dreg);
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s64 res = acc1 - acc2;
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const s64 res = acc1 - acc2;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc1, res), isOverflow(acc1, -acc2, res));
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UpdateSR64Sub(acc1, acc2, GetLongAcc(dreg));
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}
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// SUBP $acD
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@ -667,13 +653,12 @@ void Interpreter::subp(const UDSPInstruction opc)
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const s64 acc = GetLongAcc(dreg);
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const s64 prod = GetLongProduct();
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s64 res = acc - prod;
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const s64 res = acc - prod;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -prod, res));
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UpdateSR64Sub(acc, prod, GetLongAcc(dreg));
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}
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// DECM $acsD
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@ -687,13 +672,12 @@ void Interpreter::decm(const UDSPInstruction opc)
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const s64 sub = 0x10000;
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const s64 acc = GetLongAcc(dreg);
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s64 res = acc - sub;
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const s64 res = acc - sub;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -sub, res));
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UpdateSR64Sub(acc, sub, GetLongAcc(dreg));
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}
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// DEC $acD
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@ -706,13 +690,12 @@ void Interpreter::dec(const UDSPInstruction opc)
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const u8 dreg = (opc >> 8) & 0x01;
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const s64 acc = GetLongAcc(dreg);
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s64 res = acc - 1;
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const s64 res = acc - 1;
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ZeroWriteBackLog();
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry2(acc, res), isOverflow(acc, -1, res));
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UpdateSR64Sub(acc, 1, GetLongAcc(dreg));
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}
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//----
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@ -752,7 +735,7 @@ void Interpreter::abs(const UDSPInstruction opc)
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ZeroWriteBackLog();
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SetLongAcc(dreg, acc);
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UpdateSR64(GetLongAcc(dreg));
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UpdateSR64(GetLongAcc(dreg)); // TODO: Is this right?
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}
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//----
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@ -856,7 +839,7 @@ void Interpreter::lsr16(const UDSPInstruction opc)
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u64 acc = GetLongAcc(areg);
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// Lop off the extraneous sign extension our 64-bit fake accum causes
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acc &= 0x000000FFFFFFFFFFULL;
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acc &= 0x0000'00FF'FFFF'FFFFULL;
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acc >>= 16;
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ZeroWriteBackLog();
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@ -912,7 +895,7 @@ void Interpreter::lsr(const UDSPInstruction opc)
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u16 shift;
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u64 acc = GetLongAcc(rreg);
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// Lop off the extraneous sign extension our 64-bit fake accum causes
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acc &= 0x000000FFFFFFFFFFULL;
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acc &= 0x0000'00FF'FFFF'FFFFULL;
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if ((opc & 0x3f) == 0)
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shift = 0;
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@ -977,7 +960,7 @@ void Interpreter::lsrn(const UDSPInstruction opc)
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s16 shift;
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const u16 accm = static_cast<u16>(GetAccMid(1));
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u64 acc = GetLongAcc(0);
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acc &= 0x000000FFFFFFFFFFULL;
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acc &= 0x0000'00FF'FFFF'FFFFULL;
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if ((accm & 0x3f) == 0)
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shift = 0;
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@ -1046,7 +1029,7 @@ void Interpreter::lsrnrx(const UDSPInstruction opc)
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s16 shift;
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const u16 axh = state.r.ax[sreg].h;
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u64 acc = GetLongAcc(dreg);
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acc &= 0x000000FFFFFFFFFFULL;
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acc &= 0x0000'00FF'FFFF'FFFFULL;
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if ((axh & 0x3f) == 0)
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shift = 0;
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@ -1121,7 +1104,7 @@ void Interpreter::lsrnr(const UDSPInstruction opc)
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s16 shift;
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const u16 accm = static_cast<u16>(GetAccMid(1 - dreg));
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u64 acc = GetLongAcc(dreg);
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acc &= 0x000000FFFFFFFFFFULL;
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acc &= 0x0000'00FF'FFFF'FFFFULL;
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if ((accm & 0x3f) == 0)
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shift = 0;
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@ -11,18 +11,19 @@
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namespace DSP::Interpreter
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{
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constexpr bool isCarry(u64 val, u64 result)
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constexpr bool isCarryAdd(u64 val, u64 result)
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{
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return val > result;
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}
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constexpr bool isCarry2(u64 val, u64 result)
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constexpr bool isCarrySubtract(u64 val, u64 result)
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{
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return val >= result;
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}
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constexpr bool isOverflow(s64 val1, s64 val2, s64 res)
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{
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// val1 > 0 and val1 > 0 yet res < 0, or val1 < 0 and val2 < 0 yet res > 0.
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return ((val1 ^ res) & (val2 ^ res)) < 0;
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}
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@ -117,7 +117,7 @@ void Interpreter::addpaxz(const UDSPInstruction opc)
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SetLongAcc(dreg, res);
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res = GetLongAcc(dreg);
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UpdateSR64(res, isCarry(oldprod, res), false);
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UpdateSR64(res, isCarryAdd(oldprod, res), false); // TODO: Why doesn't this set the overflow bit?
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}
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//----
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@ -11,6 +11,7 @@
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#include "Core/DSP/DSPAnalyzer.h"
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#include "Core/DSP/DSPCore.h"
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#include "Core/DSP/DSPTables.h"
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#include "Core/DSP/Interpreter/DSPIntCCUtil.h"
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#include "Core/DSP/Interpreter/DSPIntTables.h"
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namespace DSP::Interpreter
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@ -547,8 +548,16 @@ void Interpreter::UpdateSR16(s16 value, bool carry, bool overflow, bool over_s32
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}
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}
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static constexpr bool IsProperlySignExtended(u64 val)
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{
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const u64 topbits = val & 0xffff'ff80'0000'0000ULL;
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return (topbits == 0) || (0xffff'ff80'0000'0000ULL == topbits);
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}
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void Interpreter::UpdateSR64(s64 value, bool carry, bool overflow)
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{
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DEBUG_ASSERT(IsProperlySignExtended(value));
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auto& state = m_dsp_core.DSPState();
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state.r.sr &= ~SR_CMP_MASK;
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@ -579,7 +588,7 @@ void Interpreter::UpdateSR64(s64 value, bool carry, bool overflow)
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}
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// 0x10
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if (value != static_cast<s32>(value))
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if (isOverS32(value))
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{
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state.r.sr |= SR_OVER_S32;
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}
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@ -591,6 +600,28 @@ void Interpreter::UpdateSR64(s64 value, bool carry, bool overflow)
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}
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}
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// Updates SR based on a 64-bit value computed by result = val1 + val2.
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// Result is a separate parameter that is properly sign-extended, and as such may not equal the
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// result of adding a and b in a 64-bit context.
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void Interpreter::UpdateSR64Add(s64 val1, s64 val2, s64 result)
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{
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DEBUG_ASSERT(((val1 + val2) & 0xff'ffff'ffffULL) == (result & 0xff'ffff'ffffULL));
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DEBUG_ASSERT(IsProperlySignExtended(val1));
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DEBUG_ASSERT(IsProperlySignExtended(val2));
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UpdateSR64(result, isCarryAdd(val1, result), isOverflow(val1, val2, result));
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}
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// Updates SR based on a 64-bit value computed by result = val1 - val2.
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// Result is a separate parameter that is properly sign-extended, and as such may not equal the
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// result of adding a and b in a 64-bit context.
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void Interpreter::UpdateSR64Sub(s64 val1, s64 val2, s64 result)
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{
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DEBUG_ASSERT(((val1 - val2) & 0xff'ffff'ffffULL) == (result & 0xff'ffff'ffffULL));
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DEBUG_ASSERT(IsProperlySignExtended(val1));
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DEBUG_ASSERT(IsProperlySignExtended(val2));
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||||
UpdateSR64(result, isCarrySubtract(val1, result), isOverflow(val1, -val2, result));
|
||||
}
|
||||
|
||||
void Interpreter::UpdateSRLogicZero(bool value)
|
||||
{
|
||||
auto& state = m_dsp_core.DSPState();
|
||||
|
|
|
|||
|
|
@ -225,6 +225,8 @@ private:
|
|||
|
||||
void UpdateSR16(s16 value, bool carry = false, bool overflow = false, bool over_s32 = false);
|
||||
void UpdateSR64(s64 value, bool carry = false, bool overflow = false);
|
||||
void UpdateSR64Add(s64 val1, s64 val2, s64 result);
|
||||
void UpdateSR64Sub(s64 val1, s64 val2, s64 result);
|
||||
void UpdateSRLogicZero(bool value);
|
||||
|
||||
u16 OpReadRegister(int reg_);
|
||||
|
|
|
|||
Loading…
Reference in New Issue