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fix crazy codegen bug and unban R12 from register allocators 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2295 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard 2009-02-17 22:18:21 +00:00
parent 73a6ae2592
commit 41ce35deb3
4 changed files with 11 additions and 13 deletions
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6
Source/Core/Common/Src/x64Emitter.cpp
View File

@ -186,7 +186,7 @@ enum NormalSSEOps
else if (scale >= 1)
{
//Ah good, no scaling.
if (scale == SCALE_ATREG && !((_offsetOrBaseReg&7) == 4 || (_offsetOrBaseReg&7) == 5))
if (scale == SCALE_ATREG && !((_offsetOrBaseReg & 7) == 4 || (_offsetOrBaseReg & 7) == 5))
{
//Okay, we're good. No SIB necessary.
int ioff = (int)offset;
@ -216,10 +216,10 @@ enum NormalSSEOps
SIB = true;
}
if (scale == SCALE_ATREG && _offsetOrBaseReg == 4)
if (scale == SCALE_ATREG && ((_offsetOrBaseReg & 7) == 4))
{
SIB = true;
ireg = 4;
ireg = _offsetOrBaseReg;
}
//Okay, we're fine. Just disp encoding.

2
Source/Core/Common/Src/x64Emitter.h
View File

@ -114,8 +114,6 @@ struct OpArg
operandReg = 0;
scale = (u8)_scale;
offsetOrBaseReg = (u8)rmReg;
if (rmReg == R12)
PanicAlert("Codegen for R12 known buggy");
indexReg = (u8)scaledReg;
//if scale == 0 never mind offseting
offset = _offset;

6
Source/Core/Core/Src/PowerPC/Jit64/JitRegCache.cpp
View File

@ -205,9 +205,9 @@ const int *GPRRegCache::GetAllocationOrder(int &count)
// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
#ifdef _M_X64
#ifdef _WIN32
RSI, RDI, R13, R14, R8, R9, R10, R11 //, RCX
RSI, RDI, R13, R14, R8, R9, R10, R11, R12, //, RCX
#else
RBP, R13, R14, R8, R9, R10, R11, //, RCX
RBP, R13, R14, R8, R9, R10, R11, R12, //, RCX
#endif
#elif _M_IX86
ESI, EDI, EBX, EBP, EDX, ECX,
@ -222,7 +222,7 @@ const int *FPURegCache::GetAllocationOrder(int &count)
static const int allocationOrder[] =
{
#ifdef _M_X64
XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5
#elif _M_IX86
XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
#endif

10
Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp
View File

@ -804,9 +804,9 @@ static void fregSpill(RegInfo& RI, X64Reg reg) {
// 64-bit - calling conventions differ between linux & windows, so...
#ifdef _WIN32
static const X64Reg RegAllocOrder[] = {RSI, RDI, R13, R14, R8, R9, R10, R11};
static const X64Reg RegAllocOrder[] = {RSI, RDI, R12, R13, R14, R8, R9, R10, R11};
#else
static const X64Reg RegAllocOrder[] = {RBP, R13, R14, R8, R9, R10, R11};
static const X64Reg RegAllocOrder[] = {RBP, R12, R13, R14, R8, R9, R10, R11};
#endif
static const int RegAllocSize = sizeof(RegAllocOrder) / sizeof(X64Reg);
static const X64Reg FRegAllocOrder[] = {XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5};
@ -1353,7 +1353,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
case StoreLink:
case StoreCTR:
case StoreMSR:
case StoreGQR:
case StoreGQR:
case StoreSRR:
case StoreFReg:
if (!isImm(*getOp1(I)))
@ -1540,10 +1540,10 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
regStoreInstToConstLoc(RI, 32, getOp1(I), &GQR(gqr));
regNormalRegClear(RI, I);
break;
}
}
case StoreSRR: {
unsigned srr = *I >> 16;
regStoreInstToConstLoc(RI, 32, getOp1(I),
regStoreInstToConstLoc(RI, 32, getOp1(I),
&PowerPC::ppcState.spr[SPR_SRR0+srr]);
regNormalRegClear(RI, I);
break;