Arm64Emitter: extract lambda to AddImmediate()
Fixes warning: ``` Source/Core/Common/Arm64Emitter.cpp:4108:31: error: declaration shadows a local variable [-Werror,-Wshadow] auto addi = [this](ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags) { ^ /var/lib/buildbot/slave/pr-android/build/Source/Core/Common/Arm64Emitter.cpp:4105:46: note: previous declaration is here void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags, ^ ```
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@ -4108,27 +4108,29 @@ void ARM64XEmitter::ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
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}
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}
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}
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}
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void ARM64XEmitter::AddImmediate(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative,
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bool flags)
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{
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switch ((negative << 1) | flags)
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{
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case 0:
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ADD(Rd, Rn, imm, shift);
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break;
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case 1:
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ADDS(Rd, Rn, imm, shift);
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break;
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case 2:
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SUB(Rd, Rn, imm, shift);
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break;
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case 3:
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SUBS(Rd, Rn, imm, shift);
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break;
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}
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}
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void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
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void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
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ARM64Reg scratch)
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ARM64Reg scratch)
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{
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{
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auto addi = [this](ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags) {
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switch ((negative << 1) | flags)
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{
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case 0:
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ADD(Rd, Rn, imm, shift);
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break;
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case 1:
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ADDS(Rd, Rn, imm, shift);
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break;
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case 2:
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SUB(Rd, Rn, imm, shift);
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break;
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case 3:
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SUBS(Rd, Rn, imm, shift);
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break;
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}
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};
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bool has_scratch = scratch != INVALID_REG;
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bool has_scratch = scratch != INVALID_REG;
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u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
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u64 imm_neg = Is64Bit(Rd) ? -imm : -imm & 0xFFFFFFFFuLL;
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bool neg_neg = negative ? false : true;
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bool neg_neg = negative ? false : true;
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@ -4137,22 +4139,22 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
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// Try them all first
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// Try them all first
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if (imm <= 0xFFF)
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if (imm <= 0xFFF)
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{
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{
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addi(Rd, Rn, imm, false, negative, flags);
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AddImmediate(Rd, Rn, imm, false, negative, flags);
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return;
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return;
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}
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}
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if (imm <= 0xFFFFFF && (imm & 0xFFF) == 0)
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if (imm <= 0xFFFFFF && (imm & 0xFFF) == 0)
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{
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{
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addi(Rd, Rn, imm >> 12, true, negative, flags);
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AddImmediate(Rd, Rn, imm >> 12, true, negative, flags);
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return;
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return;
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}
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}
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if (imm_neg <= 0xFFF)
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if (imm_neg <= 0xFFF)
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{
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{
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addi(Rd, Rn, imm_neg, false, neg_neg, flags);
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AddImmediate(Rd, Rn, imm_neg, false, neg_neg, flags);
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return;
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return;
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}
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}
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if (imm_neg <= 0xFFFFFF && (imm_neg & 0xFFF) == 0)
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if (imm_neg <= 0xFFFFFF && (imm_neg & 0xFFF) == 0)
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{
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{
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addi(Rd, Rn, imm_neg >> 12, true, neg_neg, flags);
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AddImmediate(Rd, Rn, imm_neg >> 12, true, neg_neg, flags);
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return;
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return;
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}
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}
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@ -4161,14 +4163,14 @@ void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool nega
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// As this splits the addition in two parts, this must not be done on setting flags.
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// As this splits the addition in two parts, this must not be done on setting flags.
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if (!flags && (imm >= 0x10000u || !has_scratch) && imm < 0x1000000u)
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if (!flags && (imm >= 0x10000u || !has_scratch) && imm < 0x1000000u)
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{
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{
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addi(Rd, Rn, imm & 0xFFF, false, negative, false);
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AddImmediate(Rd, Rn, imm & 0xFFF, false, negative, false);
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addi(Rd, Rd, imm >> 12, true, negative, false);
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AddImmediate(Rd, Rd, imm >> 12, true, negative, false);
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return;
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return;
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}
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}
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if (!flags && (imm_neg >= 0x10000u || !has_scratch) && imm_neg < 0x1000000u)
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if (!flags && (imm_neg >= 0x10000u || !has_scratch) && imm_neg < 0x1000000u)
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{
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{
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addi(Rd, Rn, imm_neg & 0xFFF, false, neg_neg, false);
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AddImmediate(Rd, Rn, imm_neg & 0xFFF, false, neg_neg, false);
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addi(Rd, Rd, imm_neg >> 12, true, neg_neg, false);
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AddImmediate(Rd, Rd, imm_neg >> 12, true, neg_neg, false);
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return;
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return;
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}
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}
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@ -505,6 +505,7 @@ private:
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u8* m_code;
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u8* m_code;
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u8* m_lastCacheFlushEnd;
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u8* m_lastCacheFlushEnd;
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void AddImmediate(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags);
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void EncodeCompareBranchInst(u32 op, ARM64Reg Rt, const void* ptr);
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void EncodeCompareBranchInst(u32 op, ARM64Reg Rt, const void* ptr);
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void EncodeTestBranchInst(u32 op, ARM64Reg Rt, u8 bits, const void* ptr);
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void EncodeTestBranchInst(u32 op, ARM64Reg Rt, u8 bits, const void* ptr);
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void EncodeUnconditionalBranchInst(u32 op, const void* ptr);
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void EncodeUnconditionalBranchInst(u32 op, const void* ptr);
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