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Reverted SRAM cache patch. 

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@731 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
XTra.KrazzY 2008-09-29 21:21:14 +00:00
parent ba0b277597
commit 3d25b525dd
1 changed files with 3 additions and 16 deletions
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15
Source/Core/Core/Src/HW/EXI_Channel.cpp
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@ -125,16 +125,8 @@ void CEXIChannel::Update()
}
}
bool bDirty = true;
u32 lastReg = -1, lastChan, lastVal;
void CEXIChannel::Read32(u32& _uReturnValue, const u32 _iRegister)
{
if(lastReg == _iRegister && m_ChannelId == lastChan && !bDirty) {
_uReturnValue = lastVal;
return;
}
LOG(EXPANSIONINTERFACE, "ExtensionInterface(R): channel: %i reg: %i", m_ChannelId, _iRegister);
switch (_iRegister)
@ -175,15 +167,10 @@ void CEXIChannel::Read32(u32& _uReturnValue, const u32 _iRegister)
_uReturnValue = 0xDEADBEEF;
}
lastReg = _iRegister;
lastChan = m_ChannelId;
lastVal = _uReturnValue;
bDirty = false;
}
void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
{
bDirty = true;
LOG(EXPANSIONINTERFACE, "ExtensionInterface(W): 0x%08x channel: %i reg: %i", _iValue, m_ChannelId, _iRegister);
switch (_iRegister)
@ -277,7 +264,7 @@ void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
case 1: pDevice->DMAWrite(m_DMAMemoryAddress, m_DMALength); break;
default: _dbg_assert_msg_(EXPANSIONINTERFACE,0,"EXI DMA: Unknown transfer type %i", m_Control.RW);
}
m_Control.TSTART = 0;
m_Control.TSTART = 0;
}
if(!m_Control.TSTART) // completed !