Reverted SRAM cache patch.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@731 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -125,16 +125,8 @@ void CEXIChannel::Update()
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}
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}
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}
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}
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bool bDirty = true;
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u32 lastReg = -1, lastChan, lastVal;
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void CEXIChannel::Read32(u32& _uReturnValue, const u32 _iRegister)
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void CEXIChannel::Read32(u32& _uReturnValue, const u32 _iRegister)
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{
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{
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if(lastReg == _iRegister && m_ChannelId == lastChan && !bDirty) {
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_uReturnValue = lastVal;
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return;
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}
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LOG(EXPANSIONINTERFACE, "ExtensionInterface(R): channel: %i reg: %i", m_ChannelId, _iRegister);
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LOG(EXPANSIONINTERFACE, "ExtensionInterface(R): channel: %i reg: %i", m_ChannelId, _iRegister);
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switch (_iRegister)
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switch (_iRegister)
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@ -175,15 +167,10 @@ void CEXIChannel::Read32(u32& _uReturnValue, const u32 _iRegister)
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_uReturnValue = 0xDEADBEEF;
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_uReturnValue = 0xDEADBEEF;
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}
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}
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lastReg = _iRegister;
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lastChan = m_ChannelId;
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lastVal = _uReturnValue;
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bDirty = false;
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}
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}
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void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
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void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
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{
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{
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bDirty = true;
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LOG(EXPANSIONINTERFACE, "ExtensionInterface(W): 0x%08x channel: %i reg: %i", _iValue, m_ChannelId, _iRegister);
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LOG(EXPANSIONINTERFACE, "ExtensionInterface(W): 0x%08x channel: %i reg: %i", _iValue, m_ChannelId, _iRegister);
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switch (_iRegister)
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switch (_iRegister)
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@ -277,7 +264,7 @@ void CEXIChannel::Write32(const u32 _iValue, const u32 _iRegister)
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case 1: pDevice->DMAWrite(m_DMAMemoryAddress, m_DMALength); break;
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case 1: pDevice->DMAWrite(m_DMAMemoryAddress, m_DMALength); break;
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default: _dbg_assert_msg_(EXPANSIONINTERFACE,0,"EXI DMA: Unknown transfer type %i", m_Control.RW);
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default: _dbg_assert_msg_(EXPANSIONINTERFACE,0,"EXI DMA: Unknown transfer type %i", m_Control.RW);
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}
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}
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m_Control.TSTART = 0;
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m_Control.TSTART = 0;
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}
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}
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if(!m_Control.TSTART) // completed !
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if(!m_Control.TSTART) // completed !
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