From 3ceda1df8cacb550fd92711ac0ac81e0bd1f7890 Mon Sep 17 00:00:00 2001 From: Pokechu22 Date: Tue, 7 Jun 2022 20:45:52 -0700 Subject: [PATCH] DSPLLE: Rename cr to control_reg Before, there were two distinct fields called cr and r.cr, which is needlessly confusing (see the comment in DSPCore.h). --- Source/Core/Core/DSP/DSPCore.cpp | 6 ++--- Source/Core/Core/DSP/DSPCore.h | 4 ++-- .../Core/DSP/Interpreter/DSPIntBranch.cpp | 2 +- .../Core/DSP/Interpreter/DSPInterpreter.cpp | 22 +++++++++---------- .../Core/DSP/Interpreter/DSPInterpreter.h | 4 ++-- Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp | 6 ++--- Source/Core/Core/DSP/Jit/x64/DSPEmitter.h | 2 +- Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp | 2 +- Source/Core/Core/HW/DSPLLE/DSPLLE.cpp | 4 ++-- 9 files changed, 26 insertions(+), 26 deletions(-) diff --git a/Source/Core/Core/DSP/DSPCore.cpp b/Source/Core/Core/DSP/DSPCore.cpp index e20d570fcc..9d30ea0812 100644 --- a/Source/Core/Core/DSP/DSPCore.cpp +++ b/Source/Core/Core/DSP/DSPCore.cpp @@ -161,7 +161,7 @@ bool SDSP::Initialize(const DSPInitOptions& opts) r.sr |= SR_INT_ENABLE; r.sr |= SR_EXT_INT_ENABLE; - cr = CR_INIT | CR_HALT; + control_reg = CR_INIT | CR_HALT; InitializeIFX(); // Mostly keep IRAM write protected. We unprotect only when DMA-ing // in new ucodes. @@ -210,7 +210,7 @@ void SDSP::CheckExternalInterrupt() // Signal the SPU about new mail SetException(ExceptionType::ExternalInterrupt); - cr &= ~CR_EXTERNAL_INT; + control_reg &= ~CR_EXTERNAL_INT; } void SDSP::CheckExceptions() @@ -378,7 +378,7 @@ void SDSP::DoState(PointerWrap& p) { p.Do(r); p.Do(pc); - p.Do(cr); + p.Do(control_reg); p.Do(reg_stack_ptrs); p.Do(exceptions); p.Do(external_interrupt_waiting); diff --git a/Source/Core/Core/DSP/DSPCore.h b/Source/Core/Core/DSP/DSPCore.h index 4c293fecf7..ac105922c3 100644 --- a/Source/Core/Core/DSP/DSPCore.h +++ b/Source/Core/Core/DSP/DSPCore.h @@ -419,11 +419,11 @@ struct SDSP DSP_Regs r{}; u16 pc = 0; - // This is NOT the same cr as r.cr. + // This is NOT the same as r.cr. // This register is shared with the main emulation, see DSP.cpp // The engine has control over 0x0C07 of this reg. // Bits are defined in a struct in DSP.cpp. - u16 cr = 0; + u16 control_reg = 0; u8 reg_stack_ptrs[4]{}; u8 exceptions = 0; // pending exceptions diff --git a/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp b/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp index 8b2aca8c8b..79df56479e 100644 --- a/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp +++ b/Source/Core/Core/DSP/Interpreter/DSPIntBranch.cpp @@ -127,7 +127,7 @@ void Interpreter::rti(const UDSPInstruction opc) void Interpreter::halt(const UDSPInstruction) { auto& state = m_dsp_core.DSPState(); - state.cr |= CR_HALT; + state.control_reg |= CR_HALT; state.pc--; } diff --git a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp index a2332320c8..b8478eb87a 100644 --- a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp +++ b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp @@ -81,7 +81,7 @@ int Interpreter::RunCyclesThread(int cycles) while (true) { - if ((state.cr & CR_HALT) != 0) + if ((state.control_reg & CR_HALT) != 0) return 0; if (state.external_interrupt_waiting.exchange(false, std::memory_order_acquire)) @@ -104,7 +104,7 @@ int Interpreter::RunCyclesDebug(int cycles) // First, let's run a few cycles with no idle skipping so that things can progress a bit. for (int i = 0; i < 8; i++) { - if ((state.cr & CR_HALT) != 0) + if ((state.control_reg & CR_HALT) != 0) return 0; if (m_dsp_core.BreakPoints().IsAddressBreakPoint(state.pc)) @@ -124,7 +124,7 @@ int Interpreter::RunCyclesDebug(int cycles) // idle loops. for (int i = 0; i < 8; i++) { - if ((state.cr & CR_HALT) != 0) + if ((state.control_reg & CR_HALT) != 0) return 0; if (m_dsp_core.BreakPoints().IsAddressBreakPoint(state.pc)) @@ -169,7 +169,7 @@ int Interpreter::RunCycles(int cycles) // progress a bit. for (int i = 0; i < 8; i++) { - if ((state.cr & CR_HALT) != 0) + if ((state.control_reg & CR_HALT) != 0) return 0; Step(); @@ -185,7 +185,7 @@ int Interpreter::RunCycles(int cycles) // idle loops. for (int i = 0; i < 8; i++) { - if ((state.cr & CR_HALT) != 0) + if ((state.control_reg & CR_HALT) != 0) return 0; if (state.GetAnalyzer().IsIdleSkip(state.pc)) @@ -212,7 +212,7 @@ int Interpreter::RunCycles(int cycles) } // NOTE: These have nothing to do with SDSP::r::cr! -void Interpreter::WriteCR(u16 val) +void Interpreter::WriteControlRegister(u16 val) { // reset if ((val & CR_RESET) != 0) @@ -232,23 +232,23 @@ void Interpreter::WriteCR(u16 val) } // update cr - m_dsp_core.DSPState().cr = val; + m_dsp_core.DSPState().control_reg = val; } -u16 Interpreter::ReadCR() +u16 Interpreter::ReadControlRegister() { auto& state = m_dsp_core.DSPState(); if ((state.pc & 0x8000) != 0) { - state.cr |= CR_INIT; + state.control_reg |= CR_INIT; } else { - state.cr &= ~CR_INIT; + state.control_reg &= ~CR_INIT; } - return state.cr; + return state.control_reg; } void Interpreter::SetSRFlag(u16 flag) diff --git a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.h b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.h index c6be4516b7..9fb5a9dd89 100644 --- a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.h +++ b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.h @@ -32,8 +32,8 @@ public: int RunCycles(int cycles); int RunCyclesDebug(int cycles); - void WriteCR(u16 val); - u16 ReadCR(); + void WriteControlRegister(u16 val); + u16 ReadControlRegister(); void SetSRFlag(u16 flag); bool IsSRFlagSet(u16 flag) const; diff --git a/Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp b/Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp index 4960c4c992..a8c5041dc8 100644 --- a/Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp +++ b/Source/Core/Core/DSP/Jit/x64/DSPEmitter.cpp @@ -443,7 +443,7 @@ void DSPEmitter::CompileDispatcher() } // Check for DSP halt - TEST(8, M_SDSP_cr(), Imm8(CR_HALT)); + TEST(8, M_SDSP_control_reg(), Imm8(CR_HALT)); FixupBranch _halt = J_CC(CC_NE); // Execute block. Cycles executed returned in EAX. @@ -484,9 +484,9 @@ Gen::OpArg DSPEmitter::M_SDSP_exceptions() return MDisp(R15, static_cast(offsetof(SDSP, exceptions))); } -Gen::OpArg DSPEmitter::M_SDSP_cr() +Gen::OpArg DSPEmitter::M_SDSP_control_reg() { - return MDisp(R15, static_cast(offsetof(SDSP, cr))); + return MDisp(R15, static_cast(offsetof(SDSP, control_reg))); } Gen::OpArg DSPEmitter::M_SDSP_external_interrupt_waiting() diff --git a/Source/Core/Core/DSP/Jit/x64/DSPEmitter.h b/Source/Core/Core/DSP/Jit/x64/DSPEmitter.h index 77f5eccb62..840c77cff8 100644 --- a/Source/Core/Core/DSP/Jit/x64/DSPEmitter.h +++ b/Source/Core/Core/DSP/Jit/x64/DSPEmitter.h @@ -292,7 +292,7 @@ private: // SDSP memory offset helpers Gen::OpArg M_SDSP_pc(); Gen::OpArg M_SDSP_exceptions(); - Gen::OpArg M_SDSP_cr(); + Gen::OpArg M_SDSP_control_reg(); Gen::OpArg M_SDSP_external_interrupt_waiting(); Gen::OpArg M_SDSP_r_st(size_t index); Gen::OpArg M_SDSP_reg_stack_ptrs(size_t index); diff --git a/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp b/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp index 79e2da9a91..9a5bedb4f7 100644 --- a/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp +++ b/Source/Core/Core/DSP/Jit/x64/DSPJitBranch.cpp @@ -304,7 +304,7 @@ void DSPEmitter::rti(const UDSPInstruction opc) // Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR. void DSPEmitter::halt(const UDSPInstruction) { - OR(16, M_SDSP_cr(), Imm16(CR_HALT)); + OR(16, M_SDSP_control_reg(), Imm16(CR_HALT)); // g_dsp.pc = dsp_reg_load_stack(StackRegister::Call); dsp_reg_load_stack(StackRegister::Call); MOV(16, M_SDSP_pc(), R(DX)); diff --git a/Source/Core/Core/HW/DSPLLE/DSPLLE.cpp b/Source/Core/Core/HW/DSPLLE/DSPLLE.cpp index c555ff4b9a..5f66cbd5d2 100644 --- a/Source/Core/Core/HW/DSPLLE/DSPLLE.cpp +++ b/Source/Core/Core/HW/DSPLLE/DSPLLE.cpp @@ -183,7 +183,7 @@ void DSPLLE::Shutdown() u16 DSPLLE::DSP_WriteControlRegister(u16 value) { - m_dsp_core.GetInterpreter().WriteCR(value); + m_dsp_core.GetInterpreter().WriteControlRegister(value); if ((value & CR_EXTERNAL_INT) != 0) { @@ -207,7 +207,7 @@ u16 DSPLLE::DSP_WriteControlRegister(u16 value) u16 DSPLLE::DSP_ReadControlRegister() { - return m_dsp_core.GetInterpreter().ReadCR(); + return m_dsp_core.GetInterpreter().ReadControlRegister(); } u16 DSPLLE::DSP_ReadMailBoxHigh(bool cpu_mailbox)