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JitArm64_LoadStorePaired: Use ScopedARM64Reg

This commit is contained in:
Sintendo 2024-06-23 23:18:58 +02:00
parent 23327064f6
commit 3b251dbb2a
1 changed files with 4 additions and 6 deletions
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10
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
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@ -173,20 +173,21 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
const bool have_single = fpr.IsSingle(inst.RS); const bool have_single = fpr.IsSingle(inst.RS);
ARM64Reg VS = fpr.R(inst.RS, have_single ? RegType::Single : RegType::Register); Arm64FPRCache::ScopedARM64Reg VS =
fpr.R(inst.RS, have_single ? RegType::Single : RegType::Register);
if (js.assumeNoPairedQuantize) if (js.assumeNoPairedQuantize)
{ {
if (!have_single) if (!have_single)
{ {
const ARM64Reg single_reg = fpr.GetReg(); auto single_reg = fpr.GetScopedReg();
if (w) if (w)
m_float_emit.FCVT(32, 64, EncodeRegToDouble(single_reg), EncodeRegToDouble(VS)); m_float_emit.FCVT(32, 64, EncodeRegToDouble(single_reg), EncodeRegToDouble(VS));
else else
m_float_emit.FCVTN(32, EncodeRegToDouble(single_reg), EncodeRegToDouble(VS)); m_float_emit.FCVTN(32, EncodeRegToDouble(single_reg), EncodeRegToDouble(VS));
VS = single_reg; VS = std::move(single_reg);
} }
} }
else else
@ -279,9 +280,6 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
MOV(gpr.R(inst.RA), addr_reg); MOV(gpr.R(inst.RA), addr_reg);
} }
if (js.assumeNoPairedQuantize && !have_single)
fpr.Unlock(VS);
gpr.Unlock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); gpr.Unlock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
fpr.Unlock(ARM64Reg::Q0); fpr.Unlock(ARM64Reg::Q0);
if (!js.assumeNoPairedQuantize || !jo.fastmem) if (!js.assumeNoPairedQuantize || !jo.fastmem)