DSPLLE: make ext opcodes to use table as well (tell me if you get
unknown opcodes or the like). LD changes are reverted until we get the right code. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3880 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
873190d148
commit
3b0e949c93
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#include "DSPIntUtil.h"
|
||||
#include "DSPMemoryMap.h"
|
||||
#include "DSPIntExtOps.h"
|
||||
|
||||
// Extended opcodes do not exist on their own. These opcodes can only be
|
||||
// attached to opcodes that allow extending (8 lower bits of opcode not used by
|
||||
|
|
@ -41,7 +42,6 @@
|
|||
// It's gotta be fairly simple though. See R3123, R3125 in Google Code.
|
||||
// (May have something to do with (ar[i] ^ wp[i]) == 0)
|
||||
|
||||
/*
|
||||
|
||||
namespace DSPInterpreter
|
||||
{
|
||||
|
|
@ -69,7 +69,6 @@ void ir(const UDSPInstruction& opc) {
|
|||
void nr(const UDSPInstruction& opc) {
|
||||
u8 reg = opc.hex & 0x3;
|
||||
|
||||
// g_dsp.r[reg] += g_dsp.r[reg + DSP_REG_IX0];
|
||||
dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
|
||||
}
|
||||
|
||||
|
|
@ -109,7 +108,6 @@ void sn(const UDSPInstruction& opc)
|
|||
|
||||
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
|
||||
|
||||
// g_dsp.r[dreg] += g_dsp.r[dreg + DSP_REG_IX0];
|
||||
dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
|
||||
}
|
||||
|
||||
|
|
@ -140,7 +138,208 @@ void ln(const UDSPInstruction& opc)
|
|||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
g_dsp.r[dreg] = val;
|
||||
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
}
|
||||
|
||||
// LS $(0x18+D), $acS.m
|
||||
// xxxx xxxx 10dd 000s
|
||||
// Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Increment both $ar0 and $ar3.
|
||||
void ls(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 sreg = 0x03;
|
||||
dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
|
||||
|
||||
dsp_increment_addr_reg(sreg);
|
||||
currentEpilogeFunc = ls_epi;
|
||||
}
|
||||
|
||||
void ls_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
dsp_increment_addr_reg(0x00);
|
||||
}
|
||||
|
||||
// LSN $(0x18+D), $acS.m
|
||||
// xxxx xxxx 10dd 010s
|
||||
// Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix0 to addressing
|
||||
// register $ar0 and increment $ar3.
|
||||
void lsn(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 sreg = 0x03;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
|
||||
dsp_increment_addr_reg(sreg);
|
||||
currentEpilogeFunc = lsn_epi;
|
||||
}
|
||||
|
||||
void lsn_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
}
|
||||
|
||||
// LSM $(0x18+D), $acS.m
|
||||
// xxxx xxxx 10dd 100s
|
||||
// Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix3 to addressing
|
||||
// register $ar3 and increment $ar0.
|
||||
void lsm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 sreg = 0x03;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
currentEpilogeFunc = lsm_epi;
|
||||
|
||||
}
|
||||
|
||||
void lsm_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
dsp_increment_addr_reg(0x00);
|
||||
}
|
||||
|
||||
// LSMN $(0x18+D), $acS.m
|
||||
// xxxx xxxx 10dd 110s
|
||||
// Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar0. Store value from register $acS.m to memory location pointed by
|
||||
// register $ar3. Add corresponding indexing register $ix0 to addressing
|
||||
// register $ar0 and add corresponding indexing register $ix3 to addressing
|
||||
// register $ar3.
|
||||
void lsnm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
u8 sreg = 0x03;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
currentEpilogeFunc = lsnm_epi;
|
||||
|
||||
}
|
||||
|
||||
void lsnm_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
|
||||
dsp_op_write_reg(dreg, val);
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
}
|
||||
|
||||
// SL $acS.m, $(0x18+D)
|
||||
// xxxx xxxx 10dd 001s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar3. Increment both $ar0 and $ar3.
|
||||
void sl(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_increment_addr_reg(0x00);
|
||||
currentEpilogeFunc = sl_epi;
|
||||
}
|
||||
|
||||
void sl_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
|
||||
const u8 sreg = 0x03;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
|
||||
dsp_op_write_reg(dreg, val);
|
||||
dsp_increment_addr_reg(sreg);
|
||||
}
|
||||
|
||||
// SLN $acS.m, $(0x18+D)
|
||||
// xxxx xxxx 10dd 011s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
|
||||
// and increment $ar3.
|
||||
void sln(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
currentEpilogeFunc = sln_epi;
|
||||
}
|
||||
|
||||
void sln_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
|
||||
const u8 sreg = 0x03;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
|
||||
dsp_op_write_reg(dreg, val);
|
||||
dsp_increment_addr_reg(sreg);
|
||||
}
|
||||
|
||||
// SLM $acS.m, $(0x18+D)
|
||||
// xxxx xxxx 10dd 101s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix3 to addressing register $ar3
|
||||
// and increment $ar0.
|
||||
void slm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_increment_addr_reg(0x00);
|
||||
currentEpilogeFunc = slm_epi;
|
||||
}
|
||||
|
||||
void slm_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
|
||||
const u8 sreg = 0x03;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
|
||||
dsp_op_write_reg(dreg, val);
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
}
|
||||
|
||||
// SLMN $acS.m, $(0x18+D)
|
||||
// xxxx xxxx 10dd 111s
|
||||
// Store value from register $acS.m to memory location pointed by register
|
||||
// $ar0. Load register $(0x18+D) with value from memory pointed by register
|
||||
// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
|
||||
// and add corresponding indexing register $ix3 to addressing register $ar3.
|
||||
void slnm(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
currentEpilogeFunc = slnm_epi;
|
||||
|
||||
}
|
||||
|
||||
void slnm_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
|
||||
const u8 sreg = 0x03;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
|
||||
dsp_op_write_reg(dreg, val);
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
}
|
||||
|
||||
|
|
@ -204,269 +403,11 @@ void ldnm(const UDSPInstruction& opc)
|
|||
g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
|
||||
}
|
||||
|
||||
void nop(const UDSPInstruction& opc)
|
||||
{
|
||||
}
|
||||
|
||||
} // end namespace ext
|
||||
} // end namespace DSPInterpeter
|
||||
*/
|
||||
|
||||
|
||||
void dsp_op_ext_r_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 op = (opc.hex >> 2) & 0x3;
|
||||
u8 reg = opc.hex & 0x3;
|
||||
switch (op) {
|
||||
case 0x00: //
|
||||
g_dsp.r[reg] = 0;
|
||||
break;
|
||||
|
||||
case 0x01: // DR
|
||||
dsp_decrement_addr_reg(reg);
|
||||
break;
|
||||
|
||||
case 0x02: // IR
|
||||
dsp_increment_addr_reg(reg);
|
||||
break;
|
||||
|
||||
case 0x03: // NR
|
||||
// g_dsp.r[reg] += g_dsp.r[reg + 4];
|
||||
dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_mv(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
u8 dreg = ((opc.hex >> 2) & 0x3);
|
||||
|
||||
g_dsp.r[dreg + 0x18] = g_dsp.r[sreg + 0x1c];
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_s(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = opc.hex & 0x3;
|
||||
u8 sreg = ((opc.hex >> 3) & 0x3) + 0x1c;
|
||||
|
||||
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
|
||||
|
||||
if (opc.hex & 0x04) // SN
|
||||
{
|
||||
// g_dsp.r[dreg] += g_dsp.r[dreg + 4];
|
||||
dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_increment_addr_reg(dreg); // S
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_l(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
|
||||
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
g_dsp.r[dreg] = val;
|
||||
|
||||
if (opc.hex & 0x04) // LN/LSMN
|
||||
{
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
// g_dsp.r[sreg] += g_dsp.r[sreg + 4];
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_increment_addr_reg(sreg); // LS
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_pro(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + 0x1e;
|
||||
dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
|
||||
u8 sreg = 0x03;
|
||||
|
||||
if (opc.hex & 0x8) // LSM/LSMN
|
||||
{
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else // LS
|
||||
{
|
||||
dsp_increment_addr_reg(sreg);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ls_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (opc.hex & 0x4) // LSN/LSMN
|
||||
{
|
||||
//g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
}
|
||||
else // LS
|
||||
{
|
||||
dsp_increment_addr_reg(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
void dsp_op_ext_sl_pro(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 areg = (opc.hex & 0x1) + 0x1e;
|
||||
dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
|
||||
|
||||
if (opc.hex & 0x4) // SLN/SLNM
|
||||
{
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
|
||||
// g_dsp.r[0x00] += g_dsp.r[0x04];
|
||||
}
|
||||
else // SL
|
||||
{
|
||||
dsp_increment_addr_reg(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
void dsp_op_ext_sl_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
|
||||
const u8 sreg = 0x03;
|
||||
u16 val = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
dsp_op_write_reg(dreg, val);
|
||||
|
||||
if (opc.hex & 0x8) // SLM/SLMN
|
||||
{
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
// g_dsp.r[0x03] += g_dsp.r[0x07];
|
||||
}
|
||||
else // SL
|
||||
{
|
||||
dsp_increment_addr_reg(sreg);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ld(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + 0x18;
|
||||
u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + 0x19;
|
||||
u8 sreg = opc.hex & 0x3;
|
||||
|
||||
// TODO: test the 0x00 in the else
|
||||
if (sreg != 0x3) {
|
||||
g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
|
||||
g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);
|
||||
} else {
|
||||
g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[0x00]);
|
||||
}
|
||||
|
||||
if (opc.hex & 0x04) // N
|
||||
{
|
||||
dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_increment_addr_reg(sreg);
|
||||
}
|
||||
|
||||
if (opc.hex & 0x08) // M
|
||||
{
|
||||
// TODO test
|
||||
if (sreg != 0x3)
|
||||
dsp_increase_addr_reg(0x03, (s16)g_dsp.r[DSP_REG_IX0 + 0x03]);
|
||||
else
|
||||
dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0 + 0x03]);
|
||||
}
|
||||
else
|
||||
{
|
||||
// Tested
|
||||
if (sreg != 0x3)
|
||||
dsp_increment_addr_reg(0x03);
|
||||
else
|
||||
dsp_increment_addr_reg(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ================================================================================
|
||||
//
|
||||
//
|
||||
//
|
||||
// ================================================================================
|
||||
void dsp_op_ext_ops_pro(const UDSPInstruction& opc)
|
||||
{
|
||||
if ((opc.hex & 0xFF) == 0){return;}
|
||||
|
||||
switch ((opc.hex >> 4) & 0xf)
|
||||
{
|
||||
case 0x00:
|
||||
dsp_op_ext_r_epi(opc.hex);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
dsp_op_ext_mv(opc.hex);
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
case 0x03:
|
||||
dsp_op_ext_s(opc.hex);
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
case 0x07:
|
||||
dsp_op_ext_l(opc.hex);
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
if (opc.hex & 0x2)
|
||||
dsp_op_ext_sl_pro(opc.hex);
|
||||
else
|
||||
dsp_op_ext_ls_pro(opc.hex);
|
||||
|
||||
break;
|
||||
|
||||
case 0x0c:
|
||||
case 0x0d:
|
||||
case 0x0e:
|
||||
case 0x0f:
|
||||
dsp_op_ext_ld(opc.hex);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
|
||||
{
|
||||
if ((opc.hex & 0xFF) == 0)
|
||||
return;
|
||||
|
||||
switch ((opc.hex >> 4) & 0xf)
|
||||
{
|
||||
case 0x08:
|
||||
case 0x09:
|
||||
case 0x0a:
|
||||
case 0x0b:
|
||||
if (opc.hex & 0x2)
|
||||
{
|
||||
dsp_op_ext_sl_epi(opc.hex);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsp_op_ext_ls_epi(opc.hex);
|
||||
}
|
||||
break;
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,9 +34,6 @@
|
|||
// is handled as a prologue, the ones that must be executed afterwards
|
||||
// is handled as an epilogue.
|
||||
|
||||
void dsp_op_ext_ops_pro(const UDSPInstruction& opc); // run any prologs
|
||||
void dsp_op_ext_ops_epi(const UDSPInstruction& opc); // run any epilogs
|
||||
|
||||
namespace DSPInterpreter
|
||||
{
|
||||
namespace Ext
|
||||
|
|
@ -51,12 +48,16 @@ void sl(const UDSPInstruction& opc);
|
|||
void sln(const UDSPInstruction& opc);
|
||||
void slm(const UDSPInstruction& opc);
|
||||
void slnm(const UDSPInstruction& opc);
|
||||
void ls_epi(const UDSPInstruction& opc);
|
||||
void lsn_epi(const UDSPInstruction& opc);
|
||||
void lsm_epi(const UDSPInstruction& opc);
|
||||
void lsnm_epi(const UDSPInstruction& opc);
|
||||
void sl_epi(const UDSPInstruction& opc);
|
||||
void sln_epi(const UDSPInstruction& opc);
|
||||
void slm_epi(const UDSPInstruction& opc);
|
||||
void slnm_epi(const UDSPInstruction& opc);
|
||||
void s(const UDSPInstruction& opc);
|
||||
void sn(const UDSPInstruction& opc);
|
||||
void ldx(const UDSPInstruction& opc);
|
||||
void ldxn(const UDSPInstruction& opc);
|
||||
void ldxm(const UDSPInstruction& opc);
|
||||
void ldxnm(const UDSPInstruction& opc);
|
||||
void ld(const UDSPInstruction& opc);
|
||||
void ldn(const UDSPInstruction& opc);
|
||||
void ldm(const UDSPInstruction& opc);
|
||||
|
|
@ -65,6 +66,7 @@ void mv(const UDSPInstruction& opc);
|
|||
void dr(const UDSPInstruction& opc);
|
||||
void ir(const UDSPInstruction& opc);
|
||||
void nr(const UDSPInstruction& opc);
|
||||
void nop(const UDSPInstruction& opc);
|
||||
|
||||
} // end namespace Ext
|
||||
} // end namespace DSPinterpeter
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ jnz, ifs, retlnz
|
|||
void nop(const UDSPInstruction& opc)
|
||||
{
|
||||
// The real nop is 0. Anything else is bad.
|
||||
if (opc.hex)
|
||||
if (opc.hex )
|
||||
DSPInterpreter::unknown(opc);
|
||||
}
|
||||
|
||||
|
|
@ -69,282 +69,275 @@ void nop(const UDSPInstruction& opc)
|
|||
// TODO: Fill up the tables with the corresponding instructions
|
||||
const DSPOPCTemplate opcodes[] =
|
||||
{
|
||||
{"NOP", 0x0000, 0xffff, nop, nop, 1, 0, {}, NULL, NULL},
|
||||
{"NOP", 0x0000, 0xffff, nop, nop, 1, 0, {}, false},
|
||||
|
||||
{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
|
||||
{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
|
||||
{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
|
||||
{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
|
||||
|
||||
{"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, NULL, NULL},
|
||||
{"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, false},
|
||||
|
||||
{"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RET", 0x02df, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, nop, 1, 0, {}, NULL, NULL},
|
||||
{"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RET", 0x02df, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false},
|
||||
{"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, nop, 1, 0, {}, false},
|
||||
|
||||
{"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALL", 0x02bf, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"CALL", 0x02bf, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL},
|
||||
{"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, NULL, NULL}, // This is just nop
|
||||
{"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false},
|
||||
{"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, // This is just nop
|
||||
|
||||
{"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JL", 0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JG", 0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JC", 0x0297, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JL", 0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JG", 0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JC", 0x0297, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
|
||||
{"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
|
||||
{"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
|
||||
{"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
{"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false},
|
||||
|
||||
{"SBCLR", 0x1200, 0xfff8, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, NULL, NULL},
|
||||
{"SBSET", 0x1300, 0xfff8, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, NULL, NULL},
|
||||
{"SBCLR", 0x1200, 0xfff8, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false},
|
||||
{"SBSET", 0x1300, 0xfff8, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false},
|
||||
|
||||
// actually, given the masks these should probably be 0x3f. need investigation.
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL},
|
||||
{"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL},
|
||||
{"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL},
|
||||
{"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, NULL, NULL},
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false},
|
||||
{"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false},
|
||||
{"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false},
|
||||
{"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false},
|
||||
|
||||
// discovered by ector!
|
||||
{"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, NULL, NULL},
|
||||
{"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, NULL, NULL},
|
||||
{"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, false},
|
||||
{"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, false},
|
||||
|
||||
// This one was believed to be andc'ls. Weird.
|
||||
{"LSRNR", 0x3d80, 0xfdff, DSPInterpreter::lsrnr, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, NULL, NULL},
|
||||
{"LSRNR", 0x3d80, 0xfdff, DSPInterpreter::lsrnr, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, false},
|
||||
|
||||
{"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
{"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false},
|
||||
{"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
|
||||
{"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
|
||||
{"SI", 0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"SI", 0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, NULL, NULL},
|
||||
{"SRS", 0x2800, 0xf800, DSPInterpreter::srs, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, NULL, NULL},
|
||||
{"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false},
|
||||
{"SRS", 0x2800, 0xf800, DSPInterpreter::srs, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false},
|
||||
|
||||
{"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL},
|
||||
{"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false},
|
||||
|
||||
{"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL},
|
||||
{"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL},
|
||||
{"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL,},
|
||||
{"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL,},
|
||||
{"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false},
|
||||
{"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false},
|
||||
{"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
{"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
{"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"ORF", 0x02e0, 0xfeff, DSPInterpreter::orf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL}, // Hermes: ??? (has it commented out)
|
||||
{"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
{"ORF", 0x02e0, 0xfeff, DSPInterpreter::orf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, // Hermes: ??? (has it commented out)
|
||||
|
||||
{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL}, // F|RES: missing S64
|
||||
{"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, // F|RES: missing S64
|
||||
{"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
|
||||
{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this
|
||||
{"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
|
||||
{"ILRRN", 0x0222, 0xfedc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
|
||||
{"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false}, // Hermes doesn't list this
|
||||
{"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"ILRRN", 0x0222, 0xfedc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
|
||||
// load and store value pointed by indexing reg and increment; LRR/SRR variants
|
||||
{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
|
||||
{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
|
||||
{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
|
||||
{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
|
||||
{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false},
|
||||
{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false},
|
||||
{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false},
|
||||
{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false},
|
||||
|
||||
{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
|
||||
// LOOPS
|
||||
{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
|
||||
{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL},
|
||||
{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, NULL, NULL},
|
||||
{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false},
|
||||
{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
{"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false},
|
||||
{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false},
|
||||
|
||||
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, NULL, NULL},
|
||||
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false},
|
||||
|
||||
|
||||
// opcodes that can be extended
|
||||
// extended opcodes, note size of opcode will be set to 0
|
||||
|
||||
{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, true},
|
||||
{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
|
||||
{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
|
||||
{"SET16", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SET40", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SET16", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
{"SET40", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
|
||||
|
||||
|
||||
{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"DEC", 0x7a00, 0xfeff, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOVNP", 0x7e00, 0xfeff, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
|
||||
{"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
|
||||
{"DEC", 0x7a00, 0xfeff, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MOVNP", 0x7e00, 0xfeff, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
|
||||
{"TST", 0xb100, 0xf7ff, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"TST", 0xb100, 0xf7ff, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
|
||||
|
||||
// Definitely not TSTAXL, it affects one of the accumulators. (a100 or a900, same op, one parameter).
|
||||
{"TSTAXL", 0xa100, 0xffff, DSPInterpreter::tstaxl, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"TSTAXL", 0xa100, 0xffff, DSPInterpreter::tstaxl, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
|
||||
|
||||
{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true},
|
||||
|
||||
// This op does NOT exist, at least not under this name, in duddie's docs!
|
||||
{"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
|
||||
{"CLRL", 0xfc00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
|
||||
{"CLR", 0x8100, 0xf7ff, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0
|
||||
{"CLRL", 0xfc00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0
|
||||
{"CLR", 0x8100, 0xf7ff, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, // clear acc0
|
||||
{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
|
||||
|
||||
{"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOVPZ", 0xfe00, 0xfeff, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MOVPZ", 0xfe00, 0xfeff, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"ADDPAXZ", 0xf800, 0xfcff, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, //Think the args are wrong
|
||||
{"ADDP", 0x4e00, 0xfeff, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ADDPAXZ", 0xf800, 0xfcff, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong
|
||||
{"ADDP", 0x4e00, 0xfeff, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"LSL16", 0xf000, 0xfeff, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"LSR16", 0xf400, 0xfeff, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ASR16", 0x9100, 0xf7ff, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"LSL16", 0xf000, 0xfeff, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"LSR16", 0xf400, 0xfeff, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"ASR16", 0x9100, 0xf7ff, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
|
||||
|
||||
{"XORR", 0x3000, 0xfcff, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ANDR", 0x3400, 0xfcff, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ORR", 0x3800, 0xfcff, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"XORR", 0x3000, 0xfcff, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
|
||||
{"ANDR", 0x3400, 0xfcff, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
|
||||
{"ORR", 0x3800, 0xfcff, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
|
||||
|
||||
{"MULX", 0xa000, 0xe7ff, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULXMVZ", 0xa200, 0xe6ff, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULXAC", 0xa400, 0xe6ff, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULXMV", 0xa600, 0xe6ff, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULX", 0xa000, 0xe7ff, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true},
|
||||
{"MULXMVZ", 0xa200, 0xe6ff, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXAC", 0xa400, 0xe6ff, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXMV", 0xa600, 0xe6ff, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MUL", 0x9000, 0xf7ff, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULMVZ", 0x9200, 0xf6ff, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULAC", 0x9400, 0xf6ff, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULMV", 0x9600, 0xf6ff, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MUL", 0x9000, 0xf7ff, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULMVZ", 0x9200, 0xf6ff, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULAC", 0x9400, 0xf6ff, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULMV", 0x9600, 0xf6ff, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MULC", 0xc000, 0xe7ff, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULCMVZ", 0xc200, 0xe6ff, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULCAC", 0xc400, 0xe6ff, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULCMV", 0xc600, 0xe6ff, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MULC", 0xc000, 0xe7ff, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULCMVZ", 0xc200, 0xe6ff, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCAC", 0xc400, 0xe6ff, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCMV", 0xc600, 0xe6ff, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"ADDR", 0x4000, 0xf8ff, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ADDAX", 0x4800, 0xfcff, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ADD", 0x4c00, 0xfeff, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ADDAXL", 0x7000, 0xfcff, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"ADDR", 0x4000, 0xf8ff, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"ADDAX", 0x4800, 0xfcff, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"ADD", 0x4c00, 0xfeff, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"ADDAXL", 0x7000, 0xfcff, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
|
||||
{"SUBR", 0x5000, 0xf8ff, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SUBAX", 0x5800, 0xfcff, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SUB", 0x5c00, 0xfeff, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SUBP", 0x5e00, 0xfeff, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"SUBR", 0x5000, 0xf8ff, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"SUBAX", 0x5800, 0xfcff, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"SUB", 0x5c00, 0xfeff, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"SUBP", 0x5e00, 0xfeff, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MADD", 0xf200, 0xfeff, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MSUB", 0xf600, 0xfeff, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MADDX", 0xe000, 0xfcff, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
|
||||
{"MADD", 0xf200, 0xfeff, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MSUB", 0xf600, 0xfeff, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MADDX", 0xe000, 0xfcff, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
};
|
||||
|
||||
const DSPOPCTemplate cw =
|
||||
{"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, NULL, NULL,};
|
||||
{"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false};
|
||||
|
||||
|
||||
const DSPOPCTemplate opcodes_ext[] =
|
||||
{
|
||||
// FIXME: guessing this is cr need checking
|
||||
{"DR", 0x0004, 0x00fc, nop, /*DSPInterpreter::Ext::dr*/ nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"IR", 0x0008, 0x00fc, nop, /*DSPInterpreter::Ext::ir*/ nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"NR", 0x000c, 0x00fc, nop, /*DSPInterpreter::Ext::nr*/ nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"MV", 0x0010, 0x00f0, nop, /*DSPInterpreter::Ext::mv*/ nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{
|
||||
{"XXX", 0x0000, 0x0000, nop, DSPInterpreter::Ext::nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false},
|
||||
|
||||
{"DR", 0x0004, 0x00fc, nop, DSPInterpreter::Ext::dr, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
|
||||
{"IR", 0x0008, 0x00fc, nop, DSPInterpreter::Ext::ir, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
|
||||
{"NR", 0x000c, 0x00fc, nop, DSPInterpreter::Ext::nr, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
|
||||
{"MV", 0x0010, 0x00f0, nop, DSPInterpreter::Ext::mv, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false},
|
||||
|
||||
{"S", 0x0020, 0x00e4, nop, /*DSPInterpreter::Ext::s*/ nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
|
||||
{"SN", 0x0024, 0x00e4, nop, /*DSPInterpreter::Ext::sn*/ nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, NULL, NULL,},
|
||||
{"S", 0x0020, 0x00e4, nop, DSPInterpreter::Ext::s, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false},
|
||||
{"SN", 0x0024, 0x00e4, nop, DSPInterpreter::Ext::sn, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false},
|
||||
|
||||
{"L", 0x0040, 0x00c4, nop, /*DSPInterpreter::Ext::l*/ nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"LN", 0x0044, 0x00c4, nop, /*DSPInterpreter::Ext::ln*/ nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"L", 0x0040, 0x00c4, nop, DSPInterpreter::Ext::l, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"LN", 0x0044, 0x00c4, nop, DSPInterpreter::Ext::ln, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
|
||||
{"LS", 0x0080, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
|
||||
{"SL", 0x0082, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
|
||||
{"LSN", 0x0084, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
|
||||
{"SLN", 0x0086, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
|
||||
{"LSM", 0x0088, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
|
||||
{"SLM", 0x008a, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
|
||||
{"LSNM", 0x008c, 0x00ce, nop, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, NULL, NULL,},
|
||||
{"SLNM", 0x008e, 0x00ce, nop, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, NULL, NULL,},
|
||||
{"LS", 0x0080, 0x00ce, nop, DSPInterpreter::Ext::ls, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false},
|
||||
{"SL", 0x0082, 0x00ce, nop, DSPInterpreter::Ext::sl, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false},
|
||||
{"LSN", 0x0084, 0x00ce, nop, DSPInterpreter::Ext::lsn, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false},
|
||||
{"SLN", 0x0086, 0x00ce, nop, DSPInterpreter::Ext::sln, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false},
|
||||
{"LSM", 0x0088, 0x00ce, nop, DSPInterpreter::Ext::lsm, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false},
|
||||
{"SLM", 0x008a, 0x00ce, nop, DSPInterpreter::Ext::slm, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false},
|
||||
{"LSNM", 0x008c, 0x00ce, nop, DSPInterpreter::Ext::lsnm, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false},
|
||||
{"SLNM", 0x008e, 0x00ce, nop, DSPInterpreter::Ext::slnm, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false},
|
||||
|
||||
/* FIXME: what are the LDX functions for? they have the same opcode as LD ones but different mask
|
||||
{"LDX", 0x00c0, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
|
||||
{"LDXN", 0x00c4, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
|
||||
{"LDXM", 0x00c8, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},
|
||||
{"LDXNM", 0x00cc, 0x00cf, nop, nop, 1, 3, {{P_REG18, 1, 0, 4, 0x0010}, {P_REG1A, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, NULL, NULL,},*/
|
||||
|
||||
{"LD", 0x00c0, 0x00cc, nop, /*DSPInterpreter::Ext::ld*/ nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"LDN", 0x00c4, 0x00cc, nop, /*DSPInterpreter::Ext::ldn*/ nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"LDM", 0x00c8, 0x00cc, nop, /*DSPInterpreter::Ext::ldm*/ nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
{"LDNM", 0x00cc, 0x00cc, nop, /*DSPInterpreter::Ext::ldnm*/ nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL,},
|
||||
|
||||
{"XXX", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, NULL, NULL,},
|
||||
{"LD", 0x00c0, 0x00cc, nop, DSPInterpreter::Ext::ld, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"LDN", 0x00c4, 0x00cc, nop, DSPInterpreter::Ext::ldn, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"LDM", 0x00c8, 0x00cc, nop, DSPInterpreter::Ext::ldm, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
{"LDNM", 0x00cc, 0x00cc, nop, DSPInterpreter::Ext::ldnm, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false},
|
||||
};
|
||||
|
||||
const int opcodes_size = sizeof(opcodes) / sizeof(DSPOPCTemplate);
|
||||
|
|
@ -501,8 +494,10 @@ const pdlabel_t regnames[] =
|
|||
|
||||
u8 opSize[OPTABLE_SIZE];
|
||||
dspInstFunc opTable[OPTABLE_SIZE];
|
||||
dspInstFunc prologueTable[OPTABLE_SIZE];
|
||||
dspInstFunc epilogueTable[OPTABLE_SIZE];
|
||||
dspInstFunc extOpTable[EXT_OPTABLE_SIZE];
|
||||
bool opTableUseExt[OPTABLE_SIZE];
|
||||
|
||||
dspInstFunc currentEpilogeFunc = NULL;
|
||||
|
||||
const char* pdname(u16 val)
|
||||
{
|
||||
|
|
@ -548,11 +543,30 @@ const DSPOPCTemplate *GetOpTemplate(const UDSPInstruction &inst)
|
|||
// nice property that it catches colliding op masks.
|
||||
void InitInstructionTable()
|
||||
{
|
||||
// ext op table
|
||||
for (int i = 0; i < EXT_OPTABLE_SIZE; i++)
|
||||
extOpTable[i] = DSPInterpreter::unknown;
|
||||
|
||||
for (int i = 0; i < EXT_OPTABLE_SIZE; i++)
|
||||
{
|
||||
for (int j = 0; j < opcodes_ext_size; j++)
|
||||
{
|
||||
u16 mask = opcodes_ext[j].opcode_mask;
|
||||
if ((mask & i) == opcodes_ext[j].opcode)
|
||||
{
|
||||
if (extOpTable[i] == DSPInterpreter::unknown)
|
||||
extOpTable[i] = opcodes_ext[j].interpFunc;
|
||||
else
|
||||
ERROR_LOG(DSPLLE, "opcode ext table place %d already in use for %s", i, opcodes_ext[j].name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// op table
|
||||
for (int i = 0; i < OPTABLE_SIZE; i++)
|
||||
{
|
||||
opTable[i] = DSPInterpreter::unknown;
|
||||
prologueTable[i] = NULL;
|
||||
epilogueTable[i] = NULL;
|
||||
opTableUseExt[i] = false;
|
||||
opSize[i] = 0;
|
||||
}
|
||||
|
||||
|
|
@ -571,8 +585,7 @@ void InitInstructionTable()
|
|||
{
|
||||
opTable[i] = opcodes[j].interpFunc;
|
||||
opSize[i] = opcodes[j].size & 3;
|
||||
prologueTable[i] = opcodes[j].prologue;
|
||||
epilogueTable[i] = opcodes[j].epilogue;
|
||||
opTableUseExt[i] = opcodes[j].extended;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ enum partype_t
|
|||
#define P_EXT 0x80
|
||||
|
||||
#define OPTABLE_SIZE 65536
|
||||
#define EXT_OPTABLE_SIZE 0xff
|
||||
|
||||
union UDSPInstruction
|
||||
{
|
||||
|
|
@ -114,8 +115,7 @@ typedef struct
|
|||
u8 size;
|
||||
u8 param_count;
|
||||
param2_t params[8];
|
||||
dspInstFunc prologue;
|
||||
dspInstFunc epilogue;
|
||||
bool extended;
|
||||
} DSPOPCTemplate;
|
||||
|
||||
typedef DSPOPCTemplate opc_t;
|
||||
|
|
@ -129,8 +129,10 @@ extern u8 opSize[OPTABLE_SIZE];
|
|||
extern const DSPOPCTemplate cw;
|
||||
|
||||
extern dspInstFunc opTable[];
|
||||
extern dspInstFunc prologueTable[OPTABLE_SIZE];
|
||||
extern dspInstFunc epilogueTable[OPTABLE_SIZE];
|
||||
extern bool opTableUseExt[OPTABLE_SIZE];
|
||||
extern dspInstFunc extOpTable[EXT_OPTABLE_SIZE];
|
||||
extern dspInstFunc currentEpilogeFunc;
|
||||
|
||||
|
||||
// Predefined labels
|
||||
struct pdlabel_t
|
||||
|
|
@ -152,13 +154,11 @@ void InitInstructionTable();
|
|||
|
||||
inline void ExecuteInstruction(const UDSPInstruction& inst)
|
||||
{
|
||||
// TODO: Move the prologuetable calls into the relevant instructions themselves.
|
||||
// Better not do things like this until things work correctly though.
|
||||
if (prologueTable[inst.hex])
|
||||
prologueTable[inst.hex](inst);
|
||||
if (opTableUseExt[inst.hex])
|
||||
extOpTable[inst.hex & 0xFF](inst);
|
||||
opTable[inst.hex](inst);
|
||||
if (epilogueTable[inst.hex])
|
||||
epilogueTable[inst.hex](inst);
|
||||
if (currentEpilogeFunc)
|
||||
currentEpilogeFunc(inst);
|
||||
}
|
||||
|
||||
// This one's pretty slow, try to use it only at init or seldomly.
|
||||
|
|
|
|||
|
|
@ -229,7 +229,7 @@ bool DSPDisassembler::DisOpcode(const u16 *binbuf, int base_addr, int pass, u16
|
|||
break;
|
||||
}
|
||||
}
|
||||
const DSPOPCTemplate fake_op = {"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, NULL, NULL,};
|
||||
const DSPOPCTemplate fake_op = {"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false};
|
||||
if (!opc)
|
||||
opc = &fake_op;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue