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JitArm64: Optimize FloatCompare's CR value emitting 

Setting bit 32 is only needed in the case where EQ and GT are set
but SO and LT are not, which is not a possible outcome of a compare.
This commit is contained in:
JosJuice 2021-07-12 12:34:26 +02:00
parent 8af5095ff4
commit 3af21d3d22
1 changed files with 4 additions and 7 deletions
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11
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -436,7 +436,6 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
FixupBranch pNaN, pLesser, pGreater;
FixupBranch continue1, continue2, continue3;
MOVI2R(XA, 1ULL << 32);
if (a != b)
{
@ -449,15 +448,14 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
pNaN = B(CC_VS);
// A == B
ORR(XA, XA, LogicalImm(1ULL << 63, 64));
MOVI2R(XA, 0);
if (fprf)
ORR(fpscr_reg, fpscr_reg, LogicalImm(PowerPC::CR_EQ << FPRF_SHIFT, 32));
continue1 = B();
SetJumpTarget(pNaN);
MOVI2R(XA, PowerPC::ConditionRegister::PPCToInternal(PowerPC::CR_SO));
MOVI2R(XA, ~(1ULL << PowerPC::CR_EMU_LT_BIT));
if (fprf)
ORR(fpscr_reg, fpscr_reg, LogicalImm(PowerPC::CR_SO << FPRF_SHIFT, 32));
@ -466,15 +464,14 @@ void JitArm64::FloatCompare(UGeckoInstruction inst, bool upper)
continue2 = B();
SetJumpTarget(pGreater);
ORR(XA, XA, LogicalImm(1, 64));
MOVI2R(XA, 1);
if (fprf)
ORR(fpscr_reg, fpscr_reg, LogicalImm(PowerPC::CR_GT << FPRF_SHIFT, 32));
continue3 = B();
SetJumpTarget(pLesser);
ORR(XA, XA, LogicalImm(0xC000'0000'0000'0000, 64));
ORR(XA, XA, LogicalImm(1, 64));
MOVI2R(XA, ~(1ULL << PowerPC::CR_EMU_SO_BIT));
if (fprf)
ORR(fpscr_reg, fpscr_reg, LogicalImm(PowerPC::CR_LT << FPRF_SHIFT, 32));