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Merge pull request #6492 from lioncash/nop 

Jit_Integer: Make NOP check more flexible for ori and expand NOP checking to oris, xori, and xoris
This commit is contained in:
Markus Wick 2018-03-24 08:53:21 +01:00 committed by GitHub
parent 5669841e83 fc16a78f6a
commit 3ab88742fd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 39 additions and 18 deletions
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29
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
View File

@ -304,18 +304,21 @@ void Jit64::reg_imm(UGeckoInstruction inst)
case 15: // addis
regimmop(d, a, false, (u32)inst.SIMM_16 << 16, Add, &XEmitter::ADD);
break;
case 24: // ori
if (a == 0 && s == 0 && inst.UIMM == 0 && !inst.Rc) // check for nop
case 24: // ori
case 25: // oris
{
// check for nop
if (a == s && inst.UIMM == 0)
{
// Make the nop visible in the generated code. not much use but interesting if we see one.
NOP();
return;
}
regimmop(a, s, true, inst.UIMM, Or, &XEmitter::OR);
break;
case 25: // oris
regimmop(a, s, true, inst.UIMM << 16, Or, &XEmitter::OR, false);
const u32 immediate = inst.OPCD == 24 ? inst.UIMM : inst.UIMM << 16;
regimmop(a, s, true, immediate, Or, &XEmitter::OR);
break;
}
case 28: // andi
regimmop(a, s, true, inst.UIMM, And, &XEmitter::AND, true);
break;
@ -323,11 +326,19 @@ void Jit64::reg_imm(UGeckoInstruction inst)
regimmop(a, s, true, inst.UIMM << 16, And, &XEmitter::AND, true);
break;
case 26: // xori
regimmop(a, s, true, inst.UIMM, Xor, &XEmitter::XOR, false);
break;
case 27: // xoris
regimmop(a, s, true, inst.UIMM << 16, Xor, &XEmitter::XOR, false);
{
if (s == a && inst.UIMM == 0)
{
// Make the nop visible in the generated code.
NOP();
return;
}
const u32 immediate = inst.OPCD == 26 ? inst.UIMM : inst.UIMM << 16;
regimmop(a, s, true, immediate, Xor, &XEmitter::XOR, false);
break;
}
case 12: // addic
regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, false, true);
break;

28
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -121,17 +121,20 @@ void JitArm64::arith_imm(UGeckoInstruction inst)
switch (inst.OPCD)
{
case 24: // ori
if (a == 0 && s == 0 && inst.UIMM == 0 && !inst.Rc) // check for nop
case 24: // ori
case 25: // oris
{
// check for nop
if (a == s && inst.UIMM == 0)
{
// NOP
return;
}
reg_imm(a, s, inst.UIMM, BitOR, &ARM64XEmitter::ORRI2R);
break;
case 25: // oris
reg_imm(a, s, inst.UIMM << 16, BitOR, &ARM64XEmitter::ORRI2R);
const u32 immediate = inst.OPCD == 24 ? inst.UIMM : inst.UIMM << 16;
reg_imm(a, s, immediate, BitOR, &ARM64XEmitter::ORRI2R);
break;
}
case 28: // andi
reg_imm(a, s, inst.UIMM, BitAND, &ARM64XEmitter::ANDI2R, true);
break;
@ -139,12 +142,19 @@ void JitArm64::arith_imm(UGeckoInstruction inst)
reg_imm(a, s, inst.UIMM << 16, BitAND, &ARM64XEmitter::ANDI2R, true);
break;
case 26: // xori
reg_imm(a, s, inst.UIMM, BitXOR, &ARM64XEmitter::EORI2R);
break;
case 27: // xoris
reg_imm(a, s, inst.UIMM << 16, BitXOR, &ARM64XEmitter::EORI2R);
{
if (a == s && inst.UIMM == 0)
{
// NOP
return;
}
const u32 immediate = inst.OPCD == 26 ? inst.UIMM : inst.UIMM << 16;
reg_imm(a, s, immediate, BitXOR, &ARM64XEmitter::EORI2R);
break;
}
}
}
void JitArm64::addix(UGeckoInstruction inst)