Avoid shadowing variables.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6613 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Soren Jorvang
parent
c68ae8e91e
commit
38a46ddf94
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@ -1,100 +1,100 @@
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// Copyright (C) 2003 Dolphin Project.
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// http://code.google.com/p/dolphin-emu/
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#include "Sram.h"
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#include "Sram.h"
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#include "../ConfigManager.h"
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#include "../ConfigManager.h"
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// english
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// english
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SRAM sram_dump = {{
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SRAM sram_dump = {{
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0x04, 0x6B,
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0x04, 0x6B,
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0xFB, 0x91,
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0xFB, 0x91,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0xFF, 0xFF, 0xFF, 0x40,
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0xFF, 0xFF, 0xFF, 0x40,
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0x05,
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0x05,
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0x00,
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0x00,
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0x00,
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0x00,
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0x2C,
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0x2C,
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0x44, 0x4F, 0x4C, 0x50, 0x48, 0x49, 0x4E, 0x53, 0x4C, 0x4F, 0x54, 0x41,
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0x44, 0x4F, 0x4C, 0x50, 0x48, 0x49, 0x4E, 0x53, 0x4C, 0x4F, 0x54, 0x41,
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0x44, 0x4F, 0x4C, 0x50, 0x48, 0x49, 0x4E, 0x53, 0x4C, 0x4F, 0x54, 0x42,
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0x44, 0x4F, 0x4C, 0x50, 0x48, 0x49, 0x4E, 0x53, 0x4C, 0x4F, 0x54, 0x42,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x6E, 0x6D,
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0x6E, 0x6D,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00
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0x00, 0x00
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}};
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}};
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// german
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// german
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SRAM sram_dump_german = {{
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SRAM sram_dump_german = {{
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0x1F, 0x66,
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0x1F, 0x66,
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0xE0, 0x96,
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0xE0, 0x96,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x04, 0xEA, 0x19, 0x40,
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0x04, 0xEA, 0x19, 0x40,
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0x00,
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0x00,
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0x00,
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0x00,
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0x01,
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0x01,
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0x3C,
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0x3C,
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0x12, 0xD5, 0xEA, 0xD3, 0x00, 0xFA, 0x2D, 0x33, 0x13, 0x41, 0x26, 0x03,
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0x12, 0xD5, 0xEA, 0xD3, 0x00, 0xFA, 0x2D, 0x33, 0x13, 0x41, 0x26, 0x03,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x84, 0xFF,
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0x84, 0xFF,
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0x00, 0x00,
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0x00, 0x00,
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0x00, 0x00
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0x00, 0x00
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}};
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}};
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void initSRAM()
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void initSRAM()
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{
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{
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FILE *file = fopen(SConfig::GetInstance().m_LocalCoreStartupParameter.m_strSRAM.c_str(), "rb");
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FILE *file = fopen(SConfig::GetInstance().m_LocalCoreStartupParameter.m_strSRAM.c_str(), "rb");
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if (file != NULL)
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if (file != NULL)
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{
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{
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if (fread(&g_SRAM, 1, 64, file) < 64) {
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if (fread(&g_SRAM, 1, 64, file) < 64) {
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ERROR_LOG(EXPANSIONINTERFACE, "EXI IPL-DEV: Could not read all of SRAM");
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ERROR_LOG(EXPANSIONINTERFACE, "EXI IPL-DEV: Could not read all of SRAM");
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g_SRAM = sram_dump;
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g_SRAM = sram_dump;
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}
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}
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fclose(file);
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fclose(file);
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}
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}
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else
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else
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{
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{
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g_SRAM = sram_dump;
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g_SRAM = sram_dump;
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}
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}
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}
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}
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void SetCardFlashID(u8* buffer, u8 card_index)
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void SetCardFlashID(u8* buffer, u8 card_index)
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{
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{
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u64 rand = Common::swap64( *(u64*)&(buffer[12]));
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u64 rand = Common::swap64( *(u64*)&(buffer[12]));
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u8 csum=0;
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u8 csum=0;
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for(int i = 0; i < 12; i++)
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for(int i = 0; i < 12; i++)
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{
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{
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rand = (((rand * (u64)0x0000000041c64e6dULL) + (u64)0x0000000000003039ULL) >> 16);
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rand = (((rand * (u64)0x0000000041c64e6dULL) + (u64)0x0000000000003039ULL) >> 16);
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csum += g_SRAM.flash_id[card_index][i] = buffer[i] - ((u8)rand&0xff);
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csum += g_SRAM.flash_id[card_index][i] = buffer[i] - ((u8)rand&0xff);
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rand = (((rand * (u64)0x0000000041c64e6dULL) + (u64)0x0000000000003039ULL) >> 16);
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rand = (((rand * (u64)0x0000000041c64e6dULL) + (u64)0x0000000000003039ULL) >> 16);
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rand &= (u64)0x0000000000007fffULL;
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rand &= (u64)0x0000000000007fffULL;
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}
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}
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g_SRAM.flashID_chksum[card_index] = csum^0xFF;
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g_SRAM.flashID_chksum[card_index] = csum^0xFF;
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}
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}
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File diff suppressed because it is too large
Load Diff
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@ -1,286 +1,286 @@
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// Copyright (C) 2010 Dolphin Project.
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// Copyright (C) 2010 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// http://code.google.com/p/dolphin-emu/
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#include "../DSPMemoryMap.h"
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#include "../DSPMemoryMap.h"
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#include "../DSPEmitter.h"
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#include "../DSPEmitter.h"
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#include "../DSPStacks.h"
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#include "../DSPStacks.h"
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#include "x64Emitter.h"
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#include "x64Emitter.h"
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#include "ABI.h"
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#include "ABI.h"
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using namespace Gen;
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using namespace Gen;
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const int GetCodeSize(void(*jitCode)(const UDSPInstruction, DSPEmitter&), const UDSPInstruction opc, DSPEmitter &emitter)
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const int GetCodeSize(void(*jitCode)(const UDSPInstruction, DSPEmitter&), const UDSPInstruction opc, DSPEmitter &emitter)
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{
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{
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u16 pc = g_dsp.pc;
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u16 pc = g_dsp.pc;
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const u8* ptr = emitter.GetCodePtr();
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const u8* ptr = emitter.GetCodePtr();
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jitCode(opc, emitter);
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jitCode(opc, emitter);
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//emitter.JMP(emitter.GetCodePtr());
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//emitter.JMP(emitter.GetCodePtr());
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int size = (int)(emitter.GetCodePtr() - ptr);
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int size = (int)(emitter.GetCodePtr() - ptr);
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emitter.SetCodePtr((u8*)ptr);
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emitter.SetCodePtr((u8*)ptr);
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g_dsp.pc = pc;
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g_dsp.pc = pc;
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return size;
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return size;
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}
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}
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const u8* CheckCondition(DSPEmitter& emitter, u8 cond, u8 skipCodeSize)
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const u8* CheckCondition(DSPEmitter& emitter, u8 cond, u8 skipCodeSize)
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{
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{
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if (cond == 0xf) // Always true.
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if (cond == 0xf) // Always true.
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return NULL;
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return NULL;
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//emitter.INT3();
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//emitter.INT3();
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FixupBranch skipCode2;
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FixupBranch skipCode2;
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#ifdef _M_IX86 // All32
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#ifdef _M_IX86 // All32
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emitter.MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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#else
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#else
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emitter.MOV(64, R(RAX), ImmPtr(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(64, R(RAX), ImmPtr(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(16, R(EAX), MatR(RAX));
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emitter.MOV(16, R(EAX), MatR(RAX));
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#endif
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#endif
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switch(cond)
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switch(cond)
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{
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{
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case 0x0: // GE - Greater Equal
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case 0x0: // GE - Greater Equal
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case 0x1: // L - Less
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case 0x1: // L - Less
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case 0x2: // G - Greater
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case 0x2: // G - Greater
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case 0x3: // LE - Less Equal
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case 0x3: // LE - Less Equal
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emitter.MOV(16, R(EDX), R(EAX));
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emitter.MOV(16, R(EDX), R(EAX));
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emitter.SHR(16, R(EDX), Imm8(3)); //SR_SIGN flag
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emitter.SHR(16, R(EDX), Imm8(3)); //SR_SIGN flag
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emitter.NOT(16, R(EDX));
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emitter.NOT(16, R(EDX));
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emitter.SHR(16, R(EAX), Imm8(1)); //SR_OVERFLOW flag
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emitter.SHR(16, R(EAX), Imm8(1)); //SR_OVERFLOW flag
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emitter.NOT(16, R(EAX));
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emitter.NOT(16, R(EAX));
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emitter.XOR(16, R(EAX), R(EDX));
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emitter.XOR(16, R(EAX), R(EDX));
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emitter.TEST(16, R(EAX), Imm16(1));
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emitter.TEST(16, R(EAX), Imm16(1));
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if (cond < 0x2)
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if (cond < 0x2)
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break;
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break;
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//LE: problem in here, half the tests fail
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//LE: problem in here, half the tests fail
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skipCode2 = emitter.J_CC(CC_NE);
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skipCode2 = emitter.J_CC(CC_NE);
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//skipCode2 = emitter.J_CC((CCFlags)(CC_NE - (cond & 1)));
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//skipCode2 = emitter.J_CC((CCFlags)(CC_NE - (cond & 1)));
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#ifdef _M_IX86 // All32
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#ifdef _M_IX86 // All32
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emitter.MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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#else
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#else
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emitter.MOV(64, R(RAX), ImmPtr(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(64, R(RAX), ImmPtr(&g_dsp.r[DSP_REG_SR]));
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emitter.MOV(16, R(EAX), MatR(RAX));
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emitter.MOV(16, R(EAX), MatR(RAX));
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#endif
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#endif
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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break;
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break;
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case 0x4: // NZ - Not Zero
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case 0x4: // NZ - Not Zero
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case 0x5: // Z - Zero
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case 0x5: // Z - Zero
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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break;
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break;
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case 0x6: // NC - Not carry
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case 0x6: // NC - Not carry
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case 0x7: // C - Carry
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case 0x7: // C - Carry
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emitter.TEST(16, R(EAX), Imm16(SR_CARRY));
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emitter.TEST(16, R(EAX), Imm16(SR_CARRY));
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break;
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break;
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case 0x8: // ? - Not over s32
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case 0x8: // ? - Not over s32
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case 0x9: // ? - Over s32
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case 0x9: // ? - Over s32
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emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32));
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emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32));
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break;
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break;
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case 0xa: // ?
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case 0xa: // ?
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case 0xb: // ?
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case 0xb: // ?
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{
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{
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//full of fail, both
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//full of fail, both
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emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32 | SR_TOP2BITS));
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emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32 | SR_TOP2BITS));
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FixupBranch skipArithZero = emitter.J_CC(CC_E);
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FixupBranch skipArithZero = emitter.J_CC(CC_E);
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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FixupBranch setZero = emitter.J_CC(CC_NE);
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FixupBranch setZero = emitter.J_CC(CC_NE);
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emitter.MOV(16, R(EAX), Imm16(1));
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emitter.MOV(16, R(EAX), Imm16(1));
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FixupBranch toEnd = emitter.J();
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FixupBranch toEnd = emitter.J();
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emitter.SetJumpTarget(skipArithZero);
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emitter.SetJumpTarget(skipArithZero);
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emitter.SetJumpTarget(setZero);
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emitter.SetJumpTarget(setZero);
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emitter.XOR(16, R(EAX), R(EAX));
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emitter.XOR(16, R(EAX), R(EAX));
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emitter.SetJumpTarget(toEnd);
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emitter.SetJumpTarget(toEnd);
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emitter.SETcc(CC_E, R(EAX));
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emitter.SETcc(CC_E, R(EAX));
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emitter.TEST(8, R(EAX), R(EAX));
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emitter.TEST(8, R(EAX), R(EAX));
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break;
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break;
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//emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32 | SR_TOP2BITS));
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//emitter.TEST(16, R(EAX), Imm16(SR_OVER_S32 | SR_TOP2BITS));
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//skipCode2 = emitter.J_CC((CCFlags)(CC_E + (cond & 1)));
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//skipCode2 = emitter.J_CC((CCFlags)(CC_E + (cond & 1)));
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//emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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//emitter.TEST(16, R(EAX), Imm16(SR_ARITH_ZERO));
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//break;
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//break;
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}
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}
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case 0xc: // LNZ - Logic Not Zero
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case 0xc: // LNZ - Logic Not Zero
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case 0xd: // LZ - Logic Zero
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case 0xd: // LZ - Logic Zero
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emitter.TEST(16, R(EAX), Imm16(SR_LOGIC_ZERO));
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emitter.TEST(16, R(EAX), Imm16(SR_LOGIC_ZERO));
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break;
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break;
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case 0xe: // 0 - Overflow
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case 0xe: // 0 - Overflow
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emitter.TEST(16, R(EAX), Imm16(SR_OVERFLOW));
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emitter.TEST(16, R(EAX), Imm16(SR_OVERFLOW));
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break;
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break;
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}
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}
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FixupBranch skipCode = cond == 0xe ? emitter.J_CC(CC_E) : emitter.J_CC((CCFlags)(CC_NE - (cond & 1)));
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FixupBranch skipCode = cond == 0xe ? emitter.J_CC(CC_E) : emitter.J_CC((CCFlags)(CC_NE - (cond & 1)));
|
||||||
const u8* res = emitter.GetCodePtr();
|
const u8* res = emitter.GetCodePtr();
|
||||||
emitter.NOP(skipCodeSize);
|
emitter.NOP(skipCodeSize);
|
||||||
emitter.SetJumpTarget(skipCode);
|
emitter.SetJumpTarget(skipCode);
|
||||||
if ((cond | 1) == 0x3) // || (cond | 1) == 0xb)
|
if ((cond | 1) == 0x3) // || (cond | 1) == 0xb)
|
||||||
emitter.SetJumpTarget(skipCode2);
|
emitter.SetJumpTarget(skipCode2);
|
||||||
return res;
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <void(*jitCode)(const UDSPInstruction, DSPEmitter&)>
|
template <void(*jitCode)(const UDSPInstruction, DSPEmitter&)>
|
||||||
void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
|
void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
|
||||||
{
|
{
|
||||||
static const int codeSize = GetCodeSize(jitCode, opc, emitter);
|
static const int codeSize = GetCodeSize(jitCode, opc, emitter);
|
||||||
//emitter.INT3();
|
//emitter.INT3();
|
||||||
const u8* codePtr = CheckCondition(emitter, opc & 0xf, codeSize);
|
const u8* codePtr = CheckCondition(emitter, opc & 0xf, codeSize);
|
||||||
//const u8* afterSkip = emitter.GetCodePtr();
|
//const u8* afterSkip = emitter.GetCodePtr();
|
||||||
if (codePtr != NULL)
|
if (codePtr != NULL)
|
||||||
emitter.SetCodePtr((u8*)codePtr);
|
emitter.SetCodePtr((u8*)codePtr);
|
||||||
jitCode(opc, emitter);
|
jitCode(opc, emitter);
|
||||||
//if (codePtr != NULL)
|
//if (codePtr != NULL)
|
||||||
//{
|
//{
|
||||||
// emitter.JMP(afterSkip + 4 + sizeof(void*));
|
// emitter.JMP(afterSkip + 4 + sizeof(void*));
|
||||||
// emitter.SetCodePtr((u8*)afterSkip);
|
// emitter.SetCodePtr((u8*)afterSkip);
|
||||||
// emitter.ADD(16, M(&g_dsp.pc), Imm8(1)); //4 bytes + pointer
|
// emitter.ADD(16, M(&g_dsp.pc), Imm8(1)); //4 bytes + pointer
|
||||||
//}
|
//}
|
||||||
}
|
}
|
||||||
|
|
||||||
void r_jcc(const UDSPInstruction opc, DSPEmitter& emitter)
|
void r_jcc(const UDSPInstruction opc, DSPEmitter& emitter)
|
||||||
{
|
{
|
||||||
u16 dest = dsp_imem_read(emitter.compilePC + 1);
|
u16 dest = dsp_imem_read(emitter.compilePC + 1);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest));
|
emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest));
|
||||||
|
|
||||||
// Jump directly to the called block if it has already been compiled.
|
// Jump directly to the called block if it has already been compiled.
|
||||||
// TODO: Subtract cycles from cyclesLeft
|
// TODO: Subtract cycles from cyclesLeft
|
||||||
if (emitter.blockLinks[dest])
|
if (emitter.blockLinks[dest])
|
||||||
{
|
{
|
||||||
emitter.JMPptr(M(&emitter.blockLinks[dest]));
|
emitter.JMPptr(M(&emitter.blockLinks[dest]));
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
emitter.MOV(16, MatR(RAX), Imm16(dest));
|
emitter.MOV(16, MatR(RAX), Imm16(dest));
|
||||||
|
|
||||||
// Jump directly to the next block if it has already been compiled.
|
// Jump directly to the next block if it has already been compiled.
|
||||||
// TODO: Subtract cycles from cyclesLeft
|
// TODO: Subtract cycles from cyclesLeft
|
||||||
if (emitter.blockLinks[dest])
|
if (emitter.blockLinks[dest])
|
||||||
{
|
{
|
||||||
emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest])));
|
emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest])));
|
||||||
emitter.JMPptr(R(RAX));
|
emitter.JMPptr(R(RAX));
|
||||||
emitter.ClearCallFlag();
|
emitter.ClearCallFlag();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
// Generic jmp implementation
|
// Generic jmp implementation
|
||||||
// Jcc addressA
|
// Jcc addressA
|
||||||
// 0000 0010 1001 cccc
|
// 0000 0010 1001 cccc
|
||||||
// aaaa aaaa aaaa aaaa
|
// aaaa aaaa aaaa aaaa
|
||||||
// Jump to addressA if condition cc has been met. Set program counter to
|
// Jump to addressA if condition cc has been met. Set program counter to
|
||||||
// address represented by value that follows this "jmp" instruction.
|
// address represented by value that follows this "jmp" instruction.
|
||||||
void DSPEmitter::jcc(const UDSPInstruction opc)
|
void DSPEmitter::jcc(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
// Disabled as jcc has issues in games
|
// Disabled as jcc has issues in games
|
||||||
Default(opc); return;
|
Default(opc); return;
|
||||||
#if 0
|
#if 0
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
|
MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
|
MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
|
||||||
#endif
|
#endif
|
||||||
ReJitConditional<r_jcc>(opc, *this);
|
ReJitConditional<r_jcc>(opc, *this);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void r_jmprcc(const UDSPInstruction opc, DSPEmitter& emitter)
|
void r_jmprcc(const UDSPInstruction opc, DSPEmitter& emitter)
|
||||||
{
|
{
|
||||||
u8 reg = (opc >> 5) & 0x7;
|
u8 reg = (opc >> 5) & 0x7;
|
||||||
//reg can only be DSP_REG_ARx and DSP_REG_IXx now,
|
//reg can only be DSP_REG_ARx and DSP_REG_IXx now,
|
||||||
//no need to handle DSP_REG_STx.
|
//no need to handle DSP_REG_STx.
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
emitter.MOV(16, R(EAX), M(&g_dsp.r[reg]));
|
emitter.MOV(16, R(EAX), M(&g_dsp.r[reg]));
|
||||||
emitter.MOV(16, M(&g_dsp.pc), R(EAX));
|
emitter.MOV(16, M(&g_dsp.pc), R(EAX));
|
||||||
#else
|
#else
|
||||||
emitter.MOV(64, R(RSI), ImmPtr(&g_dsp.r[reg]));
|
emitter.MOV(64, R(RSI), ImmPtr(&g_dsp.r[reg]));
|
||||||
emitter.MOV(16, R(RSI), MatR(RSI));
|
emitter.MOV(16, R(RSI), MatR(RSI));
|
||||||
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
emitter.MOV(16, MatR(RAX), R(RSI));
|
emitter.MOV(16, MatR(RAX), R(RSI));
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
// Generic jmpr implementation
|
// Generic jmpr implementation
|
||||||
// JMPcc $R
|
// JMPcc $R
|
||||||
// 0001 0111 rrr0 cccc
|
// 0001 0111 rrr0 cccc
|
||||||
// Jump to address; set program counter to a value from register $R.
|
// Jump to address; set program counter to a value from register $R.
|
||||||
void DSPEmitter::jmprcc(const UDSPInstruction opc)
|
void DSPEmitter::jmprcc(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
ReJitConditional<r_jmprcc>(opc, *this);
|
ReJitConditional<r_jmprcc>(opc, *this);
|
||||||
}
|
}
|
||||||
|
|
||||||
void r_call(const UDSPInstruction opc, DSPEmitter& emitter)
|
void r_call(const UDSPInstruction opc, DSPEmitter& emitter)
|
||||||
{
|
{
|
||||||
u16 dest = dsp_imem_read(emitter.compilePC + 1);
|
u16 dest = dsp_imem_read(emitter.compilePC + 1);
|
||||||
emitter.ABI_CallFunctionCC16((void *)dsp_reg_store_stack, DSP_STACK_C, emitter.compilePC + 2);
|
emitter.ABI_CallFunctionCC16((void *)dsp_reg_store_stack, DSP_STACK_C, emitter.compilePC + 2);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest));
|
emitter.MOV(16, M(&(g_dsp.pc)), Imm16(dest));
|
||||||
|
|
||||||
// Jump directly to the called block if it has already been compiled.
|
// Jump directly to the called block if it has already been compiled.
|
||||||
// TODO: Subtract cycles from cyclesLeft
|
// TODO: Subtract cycles from cyclesLeft
|
||||||
if (emitter.blockLinks[dest])
|
if (emitter.blockLinks[dest])
|
||||||
{
|
{
|
||||||
emitter.JMPptr(M(&emitter.blockLinks[dest]));
|
emitter.JMPptr(M(&emitter.blockLinks[dest]));
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
emitter.MOV(16, MDisp(RAX,0), Imm16(dest));
|
emitter.MOV(16, MDisp(RAX,0), Imm16(dest));
|
||||||
|
|
||||||
// Jump directly to the called block if it has already been compiled.
|
// Jump directly to the called block if it has already been compiled.
|
||||||
// TODO: Subtract cycles from cyclesLeft
|
// TODO: Subtract cycles from cyclesLeft
|
||||||
if (emitter.blockLinks[dest])
|
if (emitter.blockLinks[dest])
|
||||||
{
|
{
|
||||||
emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest])));
|
emitter.MOV(64, R(RAX), ImmPtr((void *)(emitter.blockLinks[dest])));
|
||||||
emitter.JMPptr(R(RAX));
|
emitter.JMPptr(R(RAX));
|
||||||
emitter.ClearCallFlag();
|
emitter.ClearCallFlag();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
// Generic call implementation
|
// Generic call implementation
|
||||||
// CALLcc addressA
|
// CALLcc addressA
|
||||||
// 0000 0010 1011 cccc
|
// 0000 0010 1011 cccc
|
||||||
// aaaa aaaa aaaa aaaa
|
// aaaa aaaa aaaa aaaa
|
||||||
// Call function if condition cc has been met. Push program counter of
|
// Call function if condition cc has been met. Push program counter of
|
||||||
// instruction following "call" to $st0. Set program counter to address
|
// instruction following "call" to $st0. Set program counter to address
|
||||||
// represented by value that follows this "call" instruction.
|
// represented by value that follows this "call" instruction.
|
||||||
void DSPEmitter::call(const UDSPInstruction opc)
|
void DSPEmitter::call(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
|
MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
|
MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
|
||||||
#endif
|
#endif
|
||||||
ReJitConditional<r_call>(opc, *this);
|
ReJitConditional<r_call>(opc, *this);
|
||||||
}
|
}
|
||||||
|
|
||||||
void r_callr(const UDSPInstruction opc, DSPEmitter& emitter)
|
void r_callr(const UDSPInstruction opc, DSPEmitter& emitter)
|
||||||
{
|
{
|
||||||
u8 reg = (opc >> 5) & 0x7;
|
u8 reg = (opc >> 5) & 0x7;
|
||||||
emitter.ABI_CallFunctionCC16((void *)dsp_reg_store_stack, DSP_STACK_C, emitter.compilePC + 1);
|
emitter.ABI_CallFunctionCC16((void *)dsp_reg_store_stack, DSP_STACK_C, emitter.compilePC + 1);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
emitter.MOV(16, R(EAX), M(&g_dsp.r[reg]));
|
emitter.MOV(16, R(EAX), M(&g_dsp.r[reg]));
|
||||||
emitter.MOV(16, M(&g_dsp.pc), R(EAX));
|
emitter.MOV(16, M(&g_dsp.pc), R(EAX));
|
||||||
#else
|
#else
|
||||||
emitter.MOV(64, R(RSI), ImmPtr(&g_dsp.r[reg]));
|
emitter.MOV(64, R(RSI), ImmPtr(&g_dsp.r[reg]));
|
||||||
emitter.MOV(16, R(RSI), MatR(RSI));
|
emitter.MOV(16, R(RSI), MatR(RSI));
|
||||||
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
emitter.MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
|
||||||
emitter.MOV(16, MDisp(RAX,0), R(RSI));
|
emitter.MOV(16, MDisp(RAX,0), R(RSI));
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
// Generic callr implementation
|
// Generic callr implementation
|
||||||
// CALLRcc $R
|
// CALLRcc $R
|
||||||
// 0001 0111 rrr1 cccc
|
// 0001 0111 rrr1 cccc
|
||||||
// Call function if condition cc has been met. Push program counter of
|
// Call function if condition cc has been met. Push program counter of
|
||||||
// instruction following "call" to call stack $st0. Set program counter to
|
// instruction following "call" to call stack $st0. Set program counter to
|
||||||
// register $R.
|
// register $R.
|
||||||
void DSPEmitter::callr(const UDSPInstruction opc)
|
void DSPEmitter::callr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
ReJitConditional<r_callr>(opc, *this);
|
ReJitConditional<r_callr>(opc, *this);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,367 +1,367 @@
|
||||||
// Copyright (C) 2003 Dolphin Project.
|
// Copyright (C) 2003 Dolphin Project.
|
||||||
|
|
||||||
// This program is free software: you can redistribute it and/or modify
|
// This program is free software: you can redistribute it and/or modify
|
||||||
// it under the terms of the GNU General Public License as published by
|
// it under the terms of the GNU General Public License as published by
|
||||||
// the Free Software Foundation, version 2.0.
|
// the Free Software Foundation, version 2.0.
|
||||||
|
|
||||||
// This program is distributed in the hope that it will be useful,
|
// This program is distributed in the hope that it will be useful,
|
||||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
// GNU General Public License 2.0 for more details.
|
// GNU General Public License 2.0 for more details.
|
||||||
|
|
||||||
// A copy of the GPL 2.0 should have been included with the program.
|
// A copy of the GPL 2.0 should have been included with the program.
|
||||||
// If not, see http://www.gnu.org/licenses/
|
// If not, see http://www.gnu.org/licenses/
|
||||||
|
|
||||||
// Official SVN repository and contact information can be found at
|
// Official SVN repository and contact information can be found at
|
||||||
// http://code.google.com/p/dolphin-emu/
|
// http://code.google.com/p/dolphin-emu/
|
||||||
|
|
||||||
// Additional copyrights go to Duddie and Tratax (c) 2004
|
// Additional copyrights go to Duddie and Tratax (c) 2004
|
||||||
|
|
||||||
#include "../DSPIntCCUtil.h"
|
#include "../DSPIntCCUtil.h"
|
||||||
#include "../DSPIntUtil.h"
|
#include "../DSPIntUtil.h"
|
||||||
#include "../DSPEmitter.h"
|
#include "../DSPEmitter.h"
|
||||||
#include "x64Emitter.h"
|
#include "x64Emitter.h"
|
||||||
#include "ABI.h"
|
#include "ABI.h"
|
||||||
using namespace Gen;
|
using namespace Gen;
|
||||||
|
|
||||||
// SRS @M, $(0x18+S)
|
// SRS @M, $(0x18+S)
|
||||||
// 0010 1sss mmmm mmmm
|
// 0010 1sss mmmm mmmm
|
||||||
// Move value from register $(0x18+D) to data memory pointed by address
|
// Move value from register $(0x18+D) to data memory pointed by address
|
||||||
// CR[0-7] | M. That is, the upper 8 bits of the address are the
|
// CR[0-7] | M. That is, the upper 8 bits of the address are the
|
||||||
// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
|
// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
|
||||||
// Note: pc+=2 in duddie's doc seems wrong
|
// Note: pc+=2 in duddie's doc seems wrong
|
||||||
void DSPEmitter::srs(const UDSPInstruction opc)
|
void DSPEmitter::srs(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 reg = ((opc >> 8) & 0x7) + 0x18;
|
u8 reg = ((opc >> 8) & 0x7) + 0x18;
|
||||||
//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
|
//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
||||||
MOVZX(32, 8, EAX, M(&g_dsp.r[DSP_REG_CR]));
|
MOVZX(32, 8, EAX, M(&g_dsp.r[DSP_REG_CR]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
||||||
MOVZX(64, 8, RAX, MDisp(R11,DSP_REG_CR*2));
|
MOVZX(64, 8, RAX, MDisp(R11,DSP_REG_CR*2));
|
||||||
#endif
|
#endif
|
||||||
SHL(16, R(EAX), Imm8(8));
|
SHL(16, R(EAX), Imm8(8));
|
||||||
OR(8, R(EAX), Imm8(opc & 0xFF));
|
OR(8, R(EAX), Imm8(opc & 0xFF));
|
||||||
dmem_write();
|
dmem_write();
|
||||||
}
|
}
|
||||||
|
|
||||||
// LRS $(0x18+D), @M
|
// LRS $(0x18+D), @M
|
||||||
// 0010 0ddd mmmm mmmm
|
// 0010 0ddd mmmm mmmm
|
||||||
// Move value from data memory pointed by address CR[0-7] | M to register
|
// Move value from data memory pointed by address CR[0-7] | M to register
|
||||||
// $(0x18+D). That is, the upper 8 bits of the address are the bottom 8 bits
|
// $(0x18+D). That is, the upper 8 bits of the address are the bottom 8 bits
|
||||||
// from CR, and the lower 8 bits are from the 8-bit immediate.
|
// from CR, and the lower 8 bits are from the 8-bit immediate.
|
||||||
void DSPEmitter::lrs(const UDSPInstruction opc)
|
void DSPEmitter::lrs(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 reg = ((opc >> 8) & 0x7) + 0x18;
|
u8 reg = ((opc >> 8) & 0x7) + 0x18;
|
||||||
//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
|
//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 8, ECX, M(&g_dsp.r[DSP_REG_CR]));
|
MOVZX(32, 8, ECX, M(&g_dsp.r[DSP_REG_CR]));
|
||||||
SHL(16, R(ECX), Imm8(8));
|
SHL(16, R(ECX), Imm8(8));
|
||||||
OR(8, R(ECX), Imm8(opc & 0xFF));
|
OR(8, R(ECX), Imm8(opc & 0xFF));
|
||||||
dmem_read();
|
dmem_read();
|
||||||
MOV(16, M(&g_dsp.r[reg]), R(EAX));
|
MOV(16, M(&g_dsp.r[reg]), R(EAX));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 8, RCX, MDisp(R11,DSP_REG_CR*2));
|
MOVZX(64, 8, RCX, MDisp(R11,DSP_REG_CR*2));
|
||||||
SHL(16, R(ECX), Imm8(8));
|
SHL(16, R(ECX), Imm8(8));
|
||||||
OR(8, R(ECX), Imm8(opc & 0xFF));
|
OR(8, R(ECX), Imm8(opc & 0xFF));
|
||||||
dmem_read();
|
dmem_read();
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOV(16, MDisp(R11,reg*2), R(RAX));
|
MOV(16, MDisp(R11,reg*2), R(RAX));
|
||||||
#endif
|
#endif
|
||||||
dsp_conditional_extend_accum(reg);
|
dsp_conditional_extend_accum(reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// LR $D, @M
|
// LR $D, @M
|
||||||
// 0000 0000 110d dddd
|
// 0000 0000 110d dddd
|
||||||
// mmmm mmmm mmmm mmmm
|
// mmmm mmmm mmmm mmmm
|
||||||
// Move value from data memory pointed by address M to register $D.
|
// Move value from data memory pointed by address M to register $D.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
void DSPEmitter::lr(const UDSPInstruction opc)
|
void DSPEmitter::lr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
int reg = opc & DSP_REG_MASK;
|
int reg = opc & DSP_REG_MASK;
|
||||||
u16 addr = dsp_imem_read(compilePC + 1);
|
u16 address = dsp_imem_read(compilePC + 1);
|
||||||
dmem_read_imm(addr);
|
dmem_read_imm(address);
|
||||||
dsp_op_write_reg(reg, EAX);
|
dsp_op_write_reg(reg, EAX);
|
||||||
dsp_conditional_extend_accum(reg);
|
dsp_conditional_extend_accum(reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SR @M, $S
|
// SR @M, $S
|
||||||
// 0000 0000 111s ssss
|
// 0000 0000 111s ssss
|
||||||
// mmmm mmmm mmmm mmmm
|
// mmmm mmmm mmmm mmmm
|
||||||
// Store value from register $S to a memory pointed by address M.
|
// Store value from register $S to a memory pointed by address M.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
void DSPEmitter::sr(const UDSPInstruction opc)
|
void DSPEmitter::sr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 reg = opc & DSP_REG_MASK;
|
u8 reg = opc & DSP_REG_MASK;
|
||||||
u16 addr = dsp_imem_read(compilePC + 1);
|
u16 address = dsp_imem_read(compilePC + 1);
|
||||||
dsp_op_read_reg(reg, ECX);
|
dsp_op_read_reg(reg, ECX);
|
||||||
dmem_write_imm(addr);
|
dmem_write_imm(address);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SI @M, #I
|
// SI @M, #I
|
||||||
// 0001 0110 mmmm mmmm
|
// 0001 0110 mmmm mmmm
|
||||||
// iiii iiii iiii iiii
|
// iiii iiii iiii iiii
|
||||||
// Store 16-bit immediate value I to a memory location pointed by address
|
// Store 16-bit immediate value I to a memory location pointed by address
|
||||||
// M (M is 8-bit value sign extended).
|
// M (M is 8-bit value sign extended).
|
||||||
void DSPEmitter::si(const UDSPInstruction opc)
|
void DSPEmitter::si(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u16 addr = (s8)opc;
|
u16 address = (s8)opc;
|
||||||
u16 imm = dsp_imem_read(compilePC + 1);
|
u16 imm = dsp_imem_read(compilePC + 1);
|
||||||
MOV(32, R(ECX), Imm32((u32)imm));
|
MOV(32, R(ECX), Imm32((u32)imm));
|
||||||
dmem_write_imm(addr);
|
dmem_write_imm(address);
|
||||||
}
|
}
|
||||||
|
|
||||||
// LRR $D, @$S
|
// LRR $D, @$S
|
||||||
// 0001 1000 0ssd dddd
|
// 0001 1000 0ssd dddd
|
||||||
// Move value from data memory pointed by addressing register $S to register $D.
|
// Move value from data memory pointed by addressing register $S to register $D.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
void DSPEmitter::lrr(const UDSPInstruction opc)
|
void DSPEmitter::lrr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 sreg = (opc >> 5) & 0x3;
|
u8 sreg = (opc >> 5) & 0x3;
|
||||||
u8 dreg = opc & 0x1f;
|
u8 dreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, R(ECX));
|
MOVZX(32, 16, ECX, R(ECX));
|
||||||
#else
|
#else
|
||||||
MOVZX(64, 16, ECX, R(ECX));
|
MOVZX(64, 16, ECX, R(ECX));
|
||||||
#endif
|
#endif
|
||||||
dmem_read();
|
dmem_read();
|
||||||
dsp_op_write_reg(dreg, EAX);
|
dsp_op_write_reg(dreg, EAX);
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// LRRD $D, @$S
|
// LRRD $D, @$S
|
||||||
// 0001 1000 1ssd dddd
|
// 0001 1000 1ssd dddd
|
||||||
// Move value from data memory pointed by addressing register $S toregister $D.
|
// Move value from data memory pointed by addressing register $S toregister $D.
|
||||||
// Decrement register $S.
|
// Decrement register $S.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
void DSPEmitter::lrrd(const UDSPInstruction opc)
|
void DSPEmitter::lrrd(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 sreg = (opc >> 5) & 0x3;
|
u8 sreg = (opc >> 5) & 0x3;
|
||||||
u8 dreg = opc & 0x1f;
|
u8 dreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, R(ECX));
|
MOVZX(32, 16, ECX, R(ECX));
|
||||||
#else
|
#else
|
||||||
MOVZX(64, 16, ECX, R(ECX));
|
MOVZX(64, 16, ECX, R(ECX));
|
||||||
#endif
|
#endif
|
||||||
dmem_read();
|
dmem_read();
|
||||||
dsp_op_write_reg(dreg, EAX);
|
dsp_op_write_reg(dreg, EAX);
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
decrement_addr_reg(sreg);
|
decrement_addr_reg(sreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// LRRI $D, @$S
|
// LRRI $D, @$S
|
||||||
// 0001 1001 0ssd dddd
|
// 0001 1001 0ssd dddd
|
||||||
// Move value from data memory pointed by addressing register $S to register $D.
|
// Move value from data memory pointed by addressing register $S to register $D.
|
||||||
// Increment register $S.
|
// Increment register $S.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
void DSPEmitter::lrri(const UDSPInstruction opc)
|
void DSPEmitter::lrri(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 sreg = (opc >> 5) & 0x3;
|
u8 sreg = (opc >> 5) & 0x3;
|
||||||
u8 dreg = opc & 0x1f;
|
u8 dreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, R(ECX));
|
MOVZX(32, 16, ECX, R(ECX));
|
||||||
#else
|
#else
|
||||||
MOVZX(64, 16, ECX, R(ECX));
|
MOVZX(64, 16, ECX, R(ECX));
|
||||||
#endif
|
#endif
|
||||||
dmem_read();
|
dmem_read();
|
||||||
dsp_op_write_reg(dreg, EAX);
|
dsp_op_write_reg(dreg, EAX);
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
increment_addr_reg(sreg);
|
increment_addr_reg(sreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// LRRN $D, @$S
|
// LRRN $D, @$S
|
||||||
// 0001 1001 1ssd dddd
|
// 0001 1001 1ssd dddd
|
||||||
// Move value from data memory pointed by addressing register $S to register $D.
|
// Move value from data memory pointed by addressing register $S to register $D.
|
||||||
// Add indexing register $(0x4+S) to register $S.
|
// Add indexing register $(0x4+S) to register $S.
|
||||||
// FIXME: Perform additional operation depending on destination register.
|
// FIXME: Perform additional operation depending on destination register.
|
||||||
//void DSPEmitter::lrrn(const UDSPInstruction opc)
|
//void DSPEmitter::lrrn(const UDSPInstruction opc)
|
||||||
//{
|
//{
|
||||||
// u8 sreg = (opc >> 5) & 0x3;
|
// u8 sreg = (opc >> 5) & 0x3;
|
||||||
// u8 dreg = opc & 0x1f;
|
// u8 dreg = opc & 0x1f;
|
||||||
|
|
||||||
// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
|
// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
|
||||||
// dsp_op_write_reg(dreg, val);
|
// dsp_op_write_reg(dreg, val);
|
||||||
// dsp_conditional_extend_accum(dreg);
|
// dsp_conditional_extend_accum(dreg);
|
||||||
// g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
// g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
|
||||||
//}
|
//}
|
||||||
|
|
||||||
// SRR @$D, $S
|
// SRR @$D, $S
|
||||||
// 0001 1010 0dds ssss
|
// 0001 1010 0dds ssss
|
||||||
// Store value from source register $S to a memory location pointed by
|
// Store value from source register $S to a memory location pointed by
|
||||||
// addressing register $D.
|
// addressing register $D.
|
||||||
// FIXME: Perform additional operation depending on source register.
|
// FIXME: Perform additional operation depending on source register.
|
||||||
void DSPEmitter::srr(const UDSPInstruction opc)
|
void DSPEmitter::srr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 dreg = (opc >> 5) & 0x3;
|
u8 dreg = (opc >> 5) & 0x3;
|
||||||
u8 sreg = opc & 0x1f;
|
u8 sreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
||||||
#endif
|
#endif
|
||||||
dmem_write();
|
dmem_write();
|
||||||
}
|
}
|
||||||
|
|
||||||
// SRRD @$D, $S
|
// SRRD @$D, $S
|
||||||
// 0001 1010 1dds ssss
|
// 0001 1010 1dds ssss
|
||||||
// Store value from source register $S to a memory location pointed by
|
// Store value from source register $S to a memory location pointed by
|
||||||
// addressing register $D. Decrement register $D.
|
// addressing register $D. Decrement register $D.
|
||||||
// FIXME: Perform additional operation depending on source register.
|
// FIXME: Perform additional operation depending on source register.
|
||||||
void DSPEmitter::srrd(const UDSPInstruction opc)
|
void DSPEmitter::srrd(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 dreg = (opc >> 5) & 0x3;
|
u8 dreg = (opc >> 5) & 0x3;
|
||||||
u8 sreg = opc & 0x1f;
|
u8 sreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
||||||
#endif
|
#endif
|
||||||
dmem_write();
|
dmem_write();
|
||||||
decrement_addr_reg(dreg);
|
decrement_addr_reg(dreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SRRI @$D, $S
|
// SRRI @$D, $S
|
||||||
// 0001 1011 0dds ssss
|
// 0001 1011 0dds ssss
|
||||||
// Store value from source register $S to a memory location pointed by
|
// Store value from source register $S to a memory location pointed by
|
||||||
// addressing register $D. Increment register $D.
|
// addressing register $D. Increment register $D.
|
||||||
// FIXME: Perform additional operation depending on source register.
|
// FIXME: Perform additional operation depending on source register.
|
||||||
void DSPEmitter::srri(const UDSPInstruction opc)
|
void DSPEmitter::srri(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u8 dreg = (opc >> 5) & 0x3;
|
u8 dreg = (opc >> 5) & 0x3;
|
||||||
u8 sreg = opc & 0x1f;
|
u8 sreg = opc & 0x1f;
|
||||||
|
|
||||||
dsp_op_read_reg(sreg, ECX);
|
dsp_op_read_reg(sreg, ECX);
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
|
||||||
#endif
|
#endif
|
||||||
dmem_write();
|
dmem_write();
|
||||||
increment_addr_reg(dreg);
|
increment_addr_reg(dreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SRRN @$D, $S
|
// SRRN @$D, $S
|
||||||
// 0001 1011 1dds ssss
|
// 0001 1011 1dds ssss
|
||||||
// Store value from source register $S to a memory location pointed by
|
// Store value from source register $S to a memory location pointed by
|
||||||
// addressing register $D. Add DSP_REG_IX0 register to register $D.
|
// addressing register $D. Add DSP_REG_IX0 register to register $D.
|
||||||
// FIXME: Perform additional operation depending on source register.
|
// FIXME: Perform additional operation depending on source register.
|
||||||
//void DSPEmitter::srrn(const UDSPInstruction opc)
|
//void DSPEmitter::srrn(const UDSPInstruction opc)
|
||||||
//{
|
//{
|
||||||
// u8 dreg = (opc >> 5) & 0x3;
|
// u8 dreg = (opc >> 5) & 0x3;
|
||||||
// u8 sreg = opc & 0x1f;
|
// u8 sreg = opc & 0x1f;
|
||||||
|
|
||||||
// u16 val = dsp_op_read_reg(sreg);
|
// u16 val = dsp_op_read_reg(sreg);
|
||||||
// dsp_dmem_write(g_dsp.r[dreg], val);
|
// dsp_dmem_write(g_dsp.r[dreg], val);
|
||||||
// g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
|
// g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
|
||||||
//}
|
//}
|
||||||
|
|
||||||
// ILRR $acD.m, @$arS
|
// ILRR $acD.m, @$arS
|
||||||
// 0000 001d 0001 00ss
|
// 0000 001d 0001 00ss
|
||||||
// Move value from instruction memory pointed by addressing register
|
// Move value from instruction memory pointed by addressing register
|
||||||
// $arS to mid accumulator register $acD.m.
|
// $arS to mid accumulator register $acD.m.
|
||||||
void DSPEmitter::ilrr(const UDSPInstruction opc)
|
void DSPEmitter::ilrr(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u16 reg = opc & 0x3;
|
u16 reg = opc & 0x3;
|
||||||
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||||
|
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
||||||
#endif
|
#endif
|
||||||
imem_read();
|
imem_read();
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
||||||
#endif
|
#endif
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// ILRRD $acD.m, @$arS
|
// ILRRD $acD.m, @$arS
|
||||||
// 0000 001d 0001 01ss
|
// 0000 001d 0001 01ss
|
||||||
// Move value from instruction memory pointed by addressing register
|
// Move value from instruction memory pointed by addressing register
|
||||||
// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
|
// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
|
||||||
void DSPEmitter::ilrrd(const UDSPInstruction opc)
|
void DSPEmitter::ilrrd(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u16 reg = opc & 0x3;
|
u16 reg = opc & 0x3;
|
||||||
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||||
|
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
||||||
#endif
|
#endif
|
||||||
imem_read();
|
imem_read();
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
||||||
#endif
|
#endif
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
dsp_decrement_addr_reg(reg);
|
dsp_decrement_addr_reg(reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// ILRRI $acD.m, @$S
|
// ILRRI $acD.m, @$S
|
||||||
// 0000 001d 0001 10ss
|
// 0000 001d 0001 10ss
|
||||||
// Move value from instruction memory pointed by addressing register
|
// Move value from instruction memory pointed by addressing register
|
||||||
// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
|
// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
|
||||||
void DSPEmitter::ilrri(const UDSPInstruction opc)
|
void DSPEmitter::ilrri(const UDSPInstruction opc)
|
||||||
{
|
{
|
||||||
u16 reg = opc & 0x3;
|
u16 reg = opc & 0x3;
|
||||||
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||||
|
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
||||||
#endif
|
#endif
|
||||||
imem_read();
|
imem_read();
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||||
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
||||||
#endif
|
#endif
|
||||||
dsp_conditional_extend_accum(dreg);
|
dsp_conditional_extend_accum(dreg);
|
||||||
dsp_increment_addr_reg(reg);
|
dsp_increment_addr_reg(reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
// ILRRN $acD.m, @$arS
|
// ILRRN $acD.m, @$arS
|
||||||
// 0000 001d 0001 11ss
|
// 0000 001d 0001 11ss
|
||||||
// Move value from instruction memory pointed by addressing register
|
// Move value from instruction memory pointed by addressing register
|
||||||
// $arS to mid accumulator register $acD.m. Add corresponding indexing
|
// $arS to mid accumulator register $acD.m. Add corresponding indexing
|
||||||
// register $ixS to addressing register $arS.
|
// register $ixS to addressing register $arS.
|
||||||
//void DSPEmitter::ilrrn(const UDSPInstruction opc)
|
//void DSPEmitter::ilrrn(const UDSPInstruction opc)
|
||||||
//{
|
//{
|
||||||
// u16 reg = opc & 0x3;
|
// u16 reg = opc & 0x3;
|
||||||
// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||||
|
|
||||||
// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
|
// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
|
||||||
// dsp_conditional_extend_accum(dreg);
|
// dsp_conditional_extend_accum(dreg);
|
||||||
// g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
|
// g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
|
||||||
//}
|
//}
|
||||||
|
|
||||||
//} // namespace
|
//} // namespace
|
||||||
//
|
//
|
||||||
|
|
|
||||||
|
|
@ -333,26 +333,27 @@ void DSPEmitter::dmem_write()
|
||||||
}
|
}
|
||||||
|
|
||||||
// ECX - value
|
// ECX - value
|
||||||
void DSPEmitter::dmem_write_imm(u16 addr)
|
void DSPEmitter::dmem_write_imm(u16 address)
|
||||||
{
|
{
|
||||||
switch (addr >> 12)
|
switch (address >> 12)
|
||||||
{
|
{
|
||||||
case 0x0: // 0xxx DRAM
|
case 0x0: // 0xxx DRAM
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, M(&g_dsp.dram[addr & DSP_DRAM_MASK]), R(ECX));
|
MOV(16, M(&g_dsp.dram[address & DSP_DRAM_MASK]), R(ECX));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
||||||
MOV(16, MDisp(RDX,(addr & DSP_DRAM_MASK)*2), R(ECX));
|
MOV(16, MDisp(RDX,(address & DSP_DRAM_MASK)*2), R(ECX));
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0xf: // Fxxx HW regs
|
case 0xf: // Fxxx HW regs
|
||||||
MOV(16, R(EAX), Imm16(addr));
|
MOV(16, R(EAX), Imm16(address));
|
||||||
ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX);
|
ABI_CallFunctionRR((void *)gdsp_ifx_write, EAX, ECX);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: // Unmapped/non-existing memory
|
default: // Unmapped/non-existing memory
|
||||||
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory", g_dsp.pc, addr);
|
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory",
|
||||||
|
g_dsp.pc, address);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -431,34 +432,35 @@ void DSPEmitter::dmem_read()
|
||||||
SetJumpTarget(end2);
|
SetJumpTarget(end2);
|
||||||
}
|
}
|
||||||
|
|
||||||
void DSPEmitter::dmem_read_imm(u16 addr)
|
void DSPEmitter::dmem_read_imm(u16 address)
|
||||||
{
|
{
|
||||||
switch (addr >> 12)
|
switch (address >> 12)
|
||||||
{
|
{
|
||||||
case 0x0: // 0xxx DRAM
|
case 0x0: // 0xxx DRAM
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, R(EAX), M(&g_dsp.dram[addr & DSP_DRAM_MASK]));
|
MOV(16, R(EAX), M(&g_dsp.dram[address & DSP_DRAM_MASK]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
||||||
MOV(16, R(EAX), MDisp(RDX,(addr & DSP_DRAM_MASK)*2));
|
MOV(16, R(EAX), MDisp(RDX,(address & DSP_DRAM_MASK)*2));
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x1: // 1xxx COEF
|
case 0x1: // 1xxx COEF
|
||||||
#ifdef _M_IX86 // All32
|
#ifdef _M_IX86 // All32
|
||||||
MOV(16, R(EAX), Imm16(g_dsp.coef[addr & DSP_COEF_MASK]));
|
MOV(16, R(EAX), Imm16(g_dsp.coef[address & DSP_COEF_MASK]));
|
||||||
#else
|
#else
|
||||||
MOV(64, R(RDX), ImmPtr(g_dsp.coef));
|
MOV(64, R(RDX), ImmPtr(g_dsp.coef));
|
||||||
MOV(16, R(EAX), MDisp(RDX,(addr & DSP_COEF_MASK)*2));
|
MOV(16, R(EAX), MDisp(RDX,(address & DSP_COEF_MASK)*2));
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0xf: // Fxxx HW regs
|
case 0xf: // Fxxx HW regs
|
||||||
ABI_CallFunctionC16((void *)gdsp_ifx_read, addr);
|
ABI_CallFunctionC16((void *)gdsp_ifx_read, address);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default: // Unmapped/non-existing memory
|
default: // Unmapped/non-existing memory
|
||||||
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory", g_dsp.pc, addr);
|
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory",
|
||||||
|
g_dsp.pc, address);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -98,7 +98,6 @@ void TexDecoder_OpenCL_Initialize()
|
||||||
char *header = NULL;
|
char *header = NULL;
|
||||||
size_t nDevices = 0;
|
size_t nDevices = 0;
|
||||||
cl_device_id *devices = NULL;
|
cl_device_id *devices = NULL;
|
||||||
cl_program program = NULL;
|
|
||||||
size_t *binary_sizes = NULL;
|
size_t *binary_sizes = NULL;
|
||||||
char **binaries = NULL;
|
char **binaries = NULL;
|
||||||
char filename[1024];
|
char filename[1024];
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue