From 38529a2d8de0021331e7308c5880dd0d15245a87 Mon Sep 17 00:00:00 2001 From: "Admiral H. Curtiss" Date: Mon, 9 Jan 2023 20:56:18 +0100 Subject: [PATCH] PowerPC: Parametrize DMAL macro. --- .../Interpreter/Interpreter_SystemRegisters.cpp | 10 +++++----- Source/Core/Core/PowerPC/PowerPC.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index a8e3e16d77..0316b3de81 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -390,20 +390,20 @@ void Interpreter::mtspr(UGeckoInstruction inst) case SPR_DMAL: // Locked cache<->Memory DMA // Total fake, we ignore that DMAs take time. - if (DMAL.DMA_T) + if (DMAL(PowerPC::ppcState).DMA_T) { const u32 mem_address = DMAU(PowerPC::ppcState).MEM_ADDR << 5; - const u32 cache_address = DMAL.LC_ADDR << 5; - u32 length = ((DMAU(PowerPC::ppcState).DMA_LEN_U << 2) | DMAL.DMA_LEN_L); + const u32 cache_address = DMAL(PowerPC::ppcState).LC_ADDR << 5; + u32 length = ((DMAU(PowerPC::ppcState).DMA_LEN_U << 2) | DMAL(PowerPC::ppcState).DMA_LEN_L); if (length == 0) length = 128; - if (DMAL.DMA_LD) + if (DMAL(PowerPC::ppcState).DMA_LD) PowerPC::DMA_MemoryToLC(cache_address, mem_address, length); else PowerPC::DMA_LCToMemory(mem_address, cache_address, length); } - DMAL.DMA_T = 0; + DMAL(PowerPC::ppcState).DMA_T = 0; break; case SPR_L2CR: diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h index 9c60fc4287..3e8849a2cf 100644 --- a/Source/Core/Core/PowerPC/PowerPC.h +++ b/Source/Core/Core/PowerPC/PowerPC.h @@ -239,7 +239,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst); #define HID2(ppc_state) ((UReg_HID2&)(ppc_state).spr[SPR_HID2]) #define HID4(ppc_state) ((UReg_HID4&)(ppc_state).spr[SPR_HID4]) #define DMAU(ppc_state) (*(UReg_DMAU*)&(ppc_state).spr[SPR_DMAU]) -#define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL]) +#define DMAL(ppc_state) (*(UReg_DMAL*)&(ppc_state).spr[SPR_DMAL]) #define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0]) #define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1]) #define THRM1 ((UReg_THRM12&)PowerPC::ppcState.spr[SPR_THRM1])