JitArm64: Allow ppcState STP optimization for imm
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@ -254,8 +254,12 @@ void Arm64GPRCache::FlushRegisters(BitSet32 regs, FlushMode mode, ARM64Reg tmp_r
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// We've got two guest registers in a row to store
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// We've got two guest registers in a row to store
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OpArg& reg1 = m_guest_registers[GUEST_GPR_OFFSET + i];
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OpArg& reg1 = m_guest_registers[GUEST_GPR_OFFSET + i];
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OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1];
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OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1];
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if (reg1.IsDirty() && reg2.IsDirty() && reg1.GetType() == RegType::Register &&
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const bool reg1_imm = reg1.GetType() == RegType::Immediate;
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reg2.GetType() == RegType::Register)
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const bool reg2_imm = reg2.GetType() == RegType::Immediate;
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const bool flush_all = mode == FlushMode::All;
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if (reg1.IsDirty() && reg2.IsDirty() &&
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(reg1.GetType() == RegType::Register || (reg1_imm && flush_all)) &&
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(reg2.GetType() == RegType::Register || (reg2_imm && flush_all)))
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{
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{
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const size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
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const size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
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if (ppc_offset <= 252)
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if (ppc_offset <= 252)
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@ -263,7 +267,7 @@ void Arm64GPRCache::FlushRegisters(BitSet32 regs, FlushMode mode, ARM64Reg tmp_r
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ARM64Reg RX1 = R(GetGuestByIndex(i));
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ARM64Reg RX1 = R(GetGuestByIndex(i));
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ARM64Reg RX2 = R(GetGuestByIndex(i + 1));
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ARM64Reg RX2 = R(GetGuestByIndex(i + 1));
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m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset));
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m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset));
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if (mode == FlushMode::All)
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if (flush_all)
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{
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{
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UnlockRegister(EncodeRegTo32(RX1));
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UnlockRegister(EncodeRegTo32(RX1));
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UnlockRegister(EncodeRegTo32(RX2));
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UnlockRegister(EncodeRegTo32(RX2));
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