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Jit64: boolX - Special case and with 0 

Bitwise and with zero is always zero.

Before:
45 8B F8             mov         r15d,r8d
41 83 E7 00          and         r15d,0

After:
Nothing, register a is set to constant 0.
This commit is contained in:
Sintendo 2021-01-26 22:16:00 +01:00
parent 131163d33b
commit 34dbfd92db
1 changed files with 24 additions and 18 deletions
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42
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -714,27 +714,33 @@ void Jit64::boolX(UGeckoInstruction inst)
} }
else if (is_and) else if (is_and)
{ {
RCOpArg Rj = gpr.Use(j, RCMode::Read); if (imm == 0)
RCX64Reg Ra = gpr.Bind(a, RCMode::Write); gpr.SetImmediate32(a, final_not ? 0xFFFFFFFF : 0);
RegCache::Realize(Rj, Ra);
if (complement_b)
{
if (a != j)
MOV(32, Ra, Rj);
NOT(32, Ra);
AND(32, Ra, Imm32(imm));
}
else else
{ {
if (a != j) RCOpArg Rj = gpr.Use(j, RCMode::Read);
MOV(32, Ra, Rj); RCX64Reg Ra = gpr.Bind(a, RCMode::Write);
AND(32, Ra, Imm32(imm)); RegCache::Realize(Rj, Ra);
}
if (final_not) { if (complement_b)
NOT(32, Ra); {
needs_test = true; if (a != j)
MOV(32, Ra, Rj);
NOT(32, Ra);
AND(32, Ra, Imm32(imm));
}
else
{
if (a != j)
MOV(32, Ra, Rj);
AND(32, Ra, Imm32(imm));
}
if (final_not)
{
NOT(32, Ra);
needs_test = true;
}
} }
} }
else if (is_or) else if (is_or)