Merge pull request #7386 from MerryMage/seq-points
Arm64Emitter: Remove unsequenced expressions
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commit
3405c7d420
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@ -2137,13 +2137,23 @@ void ARM64XEmitter::ABI_PushRegisters(BitSet32 registers)
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// The first push must adjust the SP, else a context switch may invalidate everything below SP.
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if (num_regs & 1)
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{
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STR(INDEX_PRE, (ARM64Reg)(X0 + *it++), SP, -stack_size);
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}
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else
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STP(INDEX_PRE, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, -stack_size);
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{
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ARM64Reg first_reg = (ARM64Reg)(X0 + *it++);
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ARM64Reg second_reg = (ARM64Reg)(X0 + *it++);
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STP(INDEX_PRE, first_reg, second_reg, SP, -stack_size);
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}
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// Fast store for all other registers, this is always an even number.
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for (int i = 0; i < (num_regs - 1) / 2; i++)
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STP(INDEX_SIGNED, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, 16 * (i + 1));
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{
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ARM64Reg odd_reg = (ARM64Reg)(X0 + *it++);
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ARM64Reg even_reg = (ARM64Reg)(X0 + *it++);
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STP(INDEX_SIGNED, odd_reg, even_reg, SP, 16 * (i + 1));
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}
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ASSERT_MSG(DYNA_REC, it == registers.end(), "%s registers don't match.", __func__);
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}
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@ -2168,7 +2178,11 @@ void ARM64XEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask)
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// Fast load for all but the first (two) registers, this is always an even number.
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for (int i = 0; i < (num_regs - 1) / 2; i++)
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LDP(INDEX_SIGNED, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, 16 * (i + 1));
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{
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ARM64Reg odd_reg = (ARM64Reg)(X0 + *it++);
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ARM64Reg even_reg = (ARM64Reg)(X0 + *it++);
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LDP(INDEX_SIGNED, odd_reg, even_reg, SP, 16 * (i + 1));
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}
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// Post loading the first (two) registers.
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if (num_regs & 1)
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