Merge pull request #6580 from lioncash/dspjitreg
DSPJitRegCache: Remove unnecessary casts in FlushRegs()
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commit
3187d1ddf6
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@ -293,21 +293,21 @@ void DSPJitRegCache::FlushRegs(DSPJitRegCache& cache, bool emit)
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for (size_t i = 0; i < m_xregs.size(); i++)
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{
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ASSERT_MSG(DSPLLE, m_xregs[i].guest_reg == cache.m_xregs[i].guest_reg,
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"cache and current xreg guest_reg mismatch for %u", static_cast<u32>(i));
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"cache and current xreg guest_reg mismatch for %zu", i);
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}
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for (size_t i = 0; i < m_regs.size(); i++)
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{
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ASSERT_MSG(DSPLLE, m_regs[i].loc.IsImm() == cache.m_regs[i].loc.IsImm(),
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"cache and current reg loc mismatch for %i", static_cast<u32>(i));
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"cache and current reg loc mismatch for %zu", i);
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ASSERT_MSG(DSPLLE, m_regs[i].loc.GetSimpleReg() == cache.m_regs[i].loc.GetSimpleReg(),
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"cache and current reg loc mismatch for %i", static_cast<u32>(i));
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"cache and current reg loc mismatch for %zu", i);
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ASSERT_MSG(DSPLLE, m_regs[i].dirty || !cache.m_regs[i].dirty,
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"cache and current reg dirty mismatch for %i", static_cast<u32>(i));
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"cache and current reg dirty mismatch for %zu", i);
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ASSERT_MSG(DSPLLE, m_regs[i].used == cache.m_regs[i].used,
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"cache and current reg used mismatch for %i", static_cast<u32>(i));
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"cache and current reg used mismatch for %zu", i);
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ASSERT_MSG(DSPLLE, m_regs[i].shift == cache.m_regs[i].shift,
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"cache and current reg shift mismatch for %i", static_cast<u32>(i));
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"cache and current reg shift mismatch for %zu", i);
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}
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m_use_ctr = cache.m_use_ctr;
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