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Merge pull request #6580 from lioncash/dspjitreg 

DSPJitRegCache: Remove unnecessary casts in FlushRegs()
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JosJuice 2018-04-01 21:53:52 +02:00 committed by GitHub
parent d8dd7b9e66 fe9d989765
commit 3187d1ddf6
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 6 deletions
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12
Source/Core/Core/DSP/Jit/x64/DSPJitRegCache.cpp
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@ -293,21 +293,21 @@ void DSPJitRegCache::FlushRegs(DSPJitRegCache& cache, bool emit)
for (size_t i = 0; i < m_xregs.size(); i++) for (size_t i = 0; i < m_xregs.size(); i++)
{ {
ASSERT_MSG(DSPLLE, m_xregs[i].guest_reg == cache.m_xregs[i].guest_reg, ASSERT_MSG(DSPLLE, m_xregs[i].guest_reg == cache.m_xregs[i].guest_reg,
"cache and current xreg guest_reg mismatch for %u", static_cast<u32>(i)); "cache and current xreg guest_reg mismatch for %zu", i);
} }
for (size_t i = 0; i < m_regs.size(); i++) for (size_t i = 0; i < m_regs.size(); i++)
{ {
ASSERT_MSG(DSPLLE, m_regs[i].loc.IsImm() == cache.m_regs[i].loc.IsImm(), ASSERT_MSG(DSPLLE, m_regs[i].loc.IsImm() == cache.m_regs[i].loc.IsImm(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i)); "cache and current reg loc mismatch for %zu", i);
ASSERT_MSG(DSPLLE, m_regs[i].loc.GetSimpleReg() == cache.m_regs[i].loc.GetSimpleReg(), ASSERT_MSG(DSPLLE, m_regs[i].loc.GetSimpleReg() == cache.m_regs[i].loc.GetSimpleReg(),
"cache and current reg loc mismatch for %i", static_cast<u32>(i)); "cache and current reg loc mismatch for %zu", i);
ASSERT_MSG(DSPLLE, m_regs[i].dirty || !cache.m_regs[i].dirty, ASSERT_MSG(DSPLLE, m_regs[i].dirty || !cache.m_regs[i].dirty,
"cache and current reg dirty mismatch for %i", static_cast<u32>(i)); "cache and current reg dirty mismatch for %zu", i);
ASSERT_MSG(DSPLLE, m_regs[i].used == cache.m_regs[i].used, ASSERT_MSG(DSPLLE, m_regs[i].used == cache.m_regs[i].used,
"cache and current reg used mismatch for %i", static_cast<u32>(i)); "cache and current reg used mismatch for %zu", i);
ASSERT_MSG(DSPLLE, m_regs[i].shift == cache.m_regs[i].shift, ASSERT_MSG(DSPLLE, m_regs[i].shift == cache.m_regs[i].shift,
"cache and current reg shift mismatch for %i", static_cast<u32>(i)); "cache and current reg shift mismatch for %zu", i);
} }
m_use_ctr = cache.m_use_ctr; m_use_ctr = cache.m_use_ctr;