JitArm64: Indexed paired loadstores workaround, attempt 2

f70ddeb did not make the issue go away.
This commit is contained in:
JosJuice 2021-08-23 10:46:28 +02:00
parent bc10412d24
commit 3071a1d13b
1 changed files with 10 additions and 8 deletions

View File

@ -39,6 +39,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1); fpr.Lock(ARM64Reg::Q0, ARM64Reg::Q1);
const ARM64Reg arm_addr = gpr.R(inst.RA);
constexpr ARM64Reg scale_reg = ARM64Reg::W0; constexpr ARM64Reg scale_reg = ARM64Reg::W0;
constexpr ARM64Reg addr_reg = ARM64Reg::W1; constexpr ARM64Reg addr_reg = ARM64Reg::W1;
constexpr ARM64Reg type_reg = ARM64Reg::W2; constexpr ARM64Reg type_reg = ARM64Reg::W2;
@ -47,11 +48,11 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
if (inst.RA || update) // Always uses the register on update if (inst.RA || update) // Always uses the register on update
{ {
if (indexed) if (indexed)
ADD(addr_reg, gpr.R(inst.RA), gpr.R(inst.RB)); ADD(addr_reg, arm_addr, gpr.R(inst.RB));
else if (offset >= 0) else if (offset >= 0)
ADD(addr_reg, gpr.R(inst.RA), offset); ADD(addr_reg, arm_addr, offset);
else else
SUB(addr_reg, gpr.R(inst.RA), std::abs(offset)); SUB(addr_reg, arm_addr, std::abs(offset));
} }
else else
{ {
@ -64,7 +65,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
if (update) if (update)
{ {
gpr.BindToRegister(inst.RA, false); gpr.BindToRegister(inst.RA, false);
MOV(gpr.R(inst.RA), addr_reg); MOV(arm_addr, addr_reg);
} }
if (js.assumeNoPairedQuantize) if (js.assumeNoPairedQuantize)
@ -162,6 +163,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30); gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
const ARM64Reg arm_addr = gpr.R(inst.RA);
constexpr ARM64Reg scale_reg = ARM64Reg::W0; constexpr ARM64Reg scale_reg = ARM64Reg::W0;
constexpr ARM64Reg addr_reg = ARM64Reg::W1; constexpr ARM64Reg addr_reg = ARM64Reg::W1;
constexpr ARM64Reg type_reg = ARM64Reg::W2; constexpr ARM64Reg type_reg = ARM64Reg::W2;
@ -176,11 +178,11 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
if (inst.RA || update) // Always uses the register on update if (inst.RA || update) // Always uses the register on update
{ {
if (indexed) if (indexed)
ADD(addr_reg, gpr.R(inst.RA), gpr.R(inst.RB)); ADD(addr_reg, arm_addr, gpr.R(inst.RB));
else if (offset >= 0) else if (offset >= 0)
ADD(addr_reg, gpr.R(inst.RA), offset); ADD(addr_reg, arm_addr, offset);
else else
SUB(addr_reg, gpr.R(inst.RA), std::abs(offset)); SUB(addr_reg, arm_addr, std::abs(offset));
} }
else else
{ {
@ -193,7 +195,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
if (update) if (update)
{ {
gpr.BindToRegister(inst.RA, false); gpr.BindToRegister(inst.RA, false);
MOV(gpr.R(inst.RA), addr_reg); MOV(arm_addr, addr_reg);
} }
if (js.assumeNoPairedQuantize) if (js.assumeNoPairedQuantize)