LLE JIT:
Applied the logic from r6691 to the LLE dec/add/sub functions so they work without ToMask. This should give a modest speedup for these. Pierre's AR inc was already perfect and I only adjusted its logic a bit for visual consistency between the interpreter and JIT code. Also applied Pierre's optimization from the LLE inc to the Int inc. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6707 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
mylek4
parent
60082853ec
commit
2f7da5d5d1
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@ -105,7 +105,7 @@ inline u16 dsp_increment_addr_reg(u16 reg)
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u32 nar = ar + 1;
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if (((nar ^ ar) & ((wr | 1) << 1)) > wr)
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if ((nar ^ ar) > ((wr | 1) << 1))
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nar -= wr + 1;
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return nar;
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}
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@ -23,140 +23,47 @@
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using namespace Gen;
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// Performs the hashing required by increment/increase/decrease_addr_reg
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// clobbers RCX
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void DSPEmitter::ToMask(X64Reg value_reg)
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{
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//microbenchmarking results(1 000 000 000 iterations):
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// cpu\variant| 1 | 2
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//intel mobile C2D@2.5GHz | 5.5s | 4.0s
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//amd athlon64x2@3GHz | 6.1s | 6.4s
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#if 0
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MOV(16, R(CX), R(value_reg));
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SHR(16, R(CX), Imm8(8));
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OR(16, R(value_reg), R(CX));
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MOV(16, R(CX), R(value_reg));
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SHR(16, R(CX), Imm8(4));
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OR(16, R(value_reg), R(CX));
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MOV(16, R(CX), R(value_reg));
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SHR(16, R(CX), Imm8(2));
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OR(16, R(value_reg), R(CX));
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MOV(16, R(CX), R(value_reg));
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SHR(16, R(CX), Imm8(1));
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OR(16, R(value_reg), R(CX));
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MOVZX(32, 16, value_reg, R(value_reg));
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#else
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BSR(16, CX, R(value_reg));
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FixupBranch undef = J_CC(CC_Z); //CX is written, but undefined
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// addr math
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//
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// These functions detect overflow by checking if
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// the bit past the top of the mask(WR) has changed in AR.
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// They detect values under the minimum for a mask by adding wr + 1
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// and checking if the bit past the top of the mask doesn't change.
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// Both are done while ignoring changes due to values/holes in IX
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// above the mask.
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MOV(32, R(value_reg), Imm32(2));
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SHL(32, R(value_reg), R(CL));
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SUB(32, R(value_reg), Imm32(1));
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//don't waste an instruction on jumping over an effective noop
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SetJumpTarget(undef);
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#endif
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OR(16, R(value_reg), Imm16(1));
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}
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// EAX = g_dsp.r[reg]
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// EDX = g_dsp.r[DSP_REG_WR0 + reg]
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//clobbers RCX
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// EAX = g_dsp.r.ar[reg]
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// EDX = g_dsp.r.wr[reg]
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// EDI = temp
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// ECX = temp
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void DSPEmitter::increment_addr_reg(int reg)
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{
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/*
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u16 ar = g_dsp.r[reg];
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u16 wr = g_dsp.r[reg+8];
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u16 nar = ar+1;
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//this works, because nar^ar will have all the bits from the highest
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//changed bit downwards set(true only for +1!)
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//based on an idea by Mylek
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if((nar^ar)>=((wr<<1)|3))
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nar -= wr+1;
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*/
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// s16 tmp = g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg]));
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MOV(16, R(DX), M(&g_dsp.r.wr[reg]));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOV(16, R(DX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
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#endif
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MOV(32, R(EDI), R(EAX));
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ADD(32, R(EAX), Imm32(1));
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XOR(32, R(EDI), R(EAX));
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MOVZX(32, 16, ESI, R(DX));
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SHL(32, R(ESI), Imm8(1));
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OR(32, R(ESI), Imm32(3));
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CMP(32, R(EDI), R(ESI));
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FixupBranch nowrap = J_CC(CC_B);
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SUB(16, R(AX), R(DX));
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SUB(16, R(AX), Imm16(1));
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SetJumpTarget(nowrap);
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// g_dsp.r[reg] = tmp;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r.ar[reg]), R(AX));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(AX));
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#endif
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}
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// EAX = g_dsp.r[reg]
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// EDX = g_dsp.r[DSP_REG_WR0 + reg]
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//clobbers RCX
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void DSPEmitter::decrement_addr_reg(int reg)
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{
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/*
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u16 ar = g_dsp.r[reg];
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u16 wr = g_dsp.r[reg+8];
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u16 m = ToMask(wr) | 1;
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u16 nar = ar-1;
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if((ar&m) - 1 < m-wr)
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nar += wr+1;
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return nar;
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*/
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// s16 ar = g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
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#endif
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// ToMask(WR0), calculating it into EDI
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//u16 m = ToMask(wr) | 1;
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MOV(32, R(EDI), R(EDX));
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ToMask(DI);
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//u32 nar = ar + 1;
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MOV(32, R(EDI), R(EAX));
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ADD(32, R(EAX), Imm8(1));
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//u16 nar = ar-1;
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MOV(16, R(CX), R(AX));
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SUB(16, R(AX), Imm16(1));
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// if ((nar ^ ar) > ((wr | 1) << 1))
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// nar -= wr + 1;
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XOR(32, R(EDI), R(EAX));
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LEA(32, ECX, MComplex(EDX, EDX, 1, 0));
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OR(32, R(ECX), Imm8(2));
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CMP(32, R(EDI), R(ECX));
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FixupBranch nowrap = J_CC(CC_BE);
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SUB(16, R(AX), R(DX));
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SUB(16, R(AX), Imm8(1));
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SetJumpTarget(nowrap);
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// g_dsp.r.ar[reg] = nar;
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//(ar&m) - 1
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AND(32, R(ECX), R(EDI)); //extension of ECX to 32 bit
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SUB(32, R(ECX), Imm32(1));
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//m-wr
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SUB(32, R(EDI), R(EDX));
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CMP(32, R(ECX), R(EDI));
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FixupBranch out1 = J_CC(CC_GE);
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ADD(16, R(AX), R(DX));
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ADD(16, R(AX), Imm16(1));
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SetJumpTarget(out1);
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// g_dsp.r[reg] = tmp;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r.ar[reg]), R(AX));
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#else
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@ -165,174 +72,176 @@ void DSPEmitter::decrement_addr_reg(int reg)
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#endif
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}
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// EAX = g_dsp.r.ar[reg]
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// EDX = g_dsp.r.wr[reg]
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// EDI = temp
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// ECX = temp
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void DSPEmitter::decrement_addr_reg(int reg)
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{
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
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#endif
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// u32 nar = ar + wr;
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// edi = nar
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LEA(32, EDI, MComplex(EAX, EDX, 1, 0));
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// if (((nar ^ ar) & ((wr | 1) << 1)) > wr)
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// nar -= wr + 1;
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XOR(32, R(EAX), R(EDI));
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LEA(32, ECX, MComplex(EDX, EDX, 1, 0));
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OR(32, R(ECX), Imm8(2));
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AND(32, R(EAX), R(ECX));
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CMP(32, R(EAX), R(EDX));
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FixupBranch nowrap = J_CC(CC_BE);
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SUB(16, R(DI), R(DX));
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SUB(16, R(DI), Imm8(1));
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SetJumpTarget(nowrap);
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// g_dsp.r.ar[reg] = nar;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r.ar[reg]), R(DI));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(DI));
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#endif
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}
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// Increase addr register according to the correspond ix register
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// EAX = g_dsp.r[reg]
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// ECX = g_dsp.r[DSP_REG_IX0 + reg]
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// EDX = g_dsp.r[DSP_REG_WR0 + reg]
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// EDI = tomask(EDX)
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// EAX = g_dsp.r.ar[reg]
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// EDX = g_dsp.r.wr[reg]
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// ESI = g_dsp.r.ix[reg]
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// ECX = temp
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// EDI = temp
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void DSPEmitter::increase_addr_reg(int reg)
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{
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/*
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u16 ar = g_dsp.r[reg];
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u16 wr = g_dsp.r[reg+8];
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u16 ix = g_dsp.r[reg+4];
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u16 m = ToMask(wr) | 1;
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u16 nar = ar+ix;
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if ((s16)ix >= 0) {
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if((ar&m) + (ix&m) -(int)m-1 >= 0)
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nar -= wr+1;
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} else {
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if((ar&m) + (ix&m) -(int)m-1 < m-wr)
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nar += wr+1;
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}
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return nar;
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*/
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#ifdef _M_IX86 // All32
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MOV(16, R(SI), M(&g_dsp.r.ix[reg]));
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MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
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MOVSX(32, 16, ESI, M(&g_dsp.r.ix[reg]));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, R(SI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
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MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
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MOVSX(32, 16, ESI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
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#endif
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// ToMask(WR0), calculating it into EDI
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//u16 m = ToMask(wr) | 1;
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MOV(32, R(EDI), R(EDX));
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ToMask(DI);
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//u32 nar = ar + ix;
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//edi = nar
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LEA(32, EDI, MComplex(EAX, ESI, 1, 0));
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//u16 nar = ar+ix;
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MOV(16, R(CX), R(AX));
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ADD(16, R(AX), R(SI));
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//u32 dar = (nar ^ ar ^ ix) & ((wr | 1) << 1);
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//eax = dar
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XOR(32, R(EAX), R(ESI));
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XOR(32, R(EAX), R(EDI));
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LEA(32, ECX, MComplex(EDX, EDX, 1, 0));
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OR(32, R(ECX), Imm8(2));
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AND(32, R(EAX), R(ECX));
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TEST(16, R(SI), Imm16(0x8000));
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FixupBranch negative = J_CC(CC_NZ);
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//(ar&m) + (ix&m) -(int)m-1
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AND(32, R(ECX), R(EDI)); //extension of ECX to 32 bit
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AND(32, R(ESI), R(EDI)); //extension of ESI to 32 bit
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ADD(32, R(ECX), R(ESI));
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SUB(32, R(ECX), R(EDI));
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SUB(32, R(ECX), Imm32(1));
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CMP(32, R(ECX), Imm32(0));
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FixupBranch out1 = J_CC(CC_L);
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SUB(16, R(AX), R(DX));
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SUB(16, R(AX), Imm16(1));
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FixupBranch out2 = J();
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//if (ix >= 0)
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TEST(32, R(ESI), R(ESI));
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FixupBranch negative = J_CC(CC_S);
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//if (dar > wr)
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CMP(32, R(EAX), R(EDX));
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FixupBranch done = J_CC(CC_BE);
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//nar -= wr + 1;
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SUB(16, R(DI), R(DX));
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SUB(16, R(DI), Imm8(1));
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FixupBranch done2 = J();
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//else
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SetJumpTarget(negative);
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//if ((((nar + wr + 1) ^ nar) & dar) <= wr)
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LEA(32, ECX, MComplex(EDI, EDX, 1, 1));
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XOR(32, R(ECX), R(EDI));
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AND(32, R(ECX), R(EAX));
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CMP(32, R(ECX), R(EDX));
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FixupBranch done3 = J_CC(CC_A);
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//nar += wr + 1;
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LEA(16, DI, MComplex(DI, DX, 1, 1));
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//(ar&m) + (ix&m) -(int)m-1
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AND(32, R(ECX), R(EDI)); //extension of ECX to 32 bit
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AND(32, R(ESI), R(EDI)); //extension of ESI to 32 bit
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ADD(32, R(ECX), R(ESI));
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SUB(32, R(ECX), R(EDI));
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SUB(32, R(ECX), Imm32(1));
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//m-wr
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SUB(32, R(EDI), R(EDX));
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CMP(32, R(ECX), R(EDI));
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FixupBranch out3 = J_CC(CC_GE);
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ADD(16, R(AX), R(DX));
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ADD(16, R(AX), Imm16(1));
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SetJumpTarget(done);
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SetJumpTarget(done2);
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SetJumpTarget(done3);
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// g_dsp.r.ar[reg] = nar;
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SetJumpTarget(out1);
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SetJumpTarget(out2);
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SetJumpTarget(out3);
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// g_dsp.r[reg] = tmp;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r.ar[reg]), R(EAX));
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MOV(16, M(&g_dsp.r.ar[reg]), R(DI));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX));
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MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(DI));
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#endif
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}
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// Decrease addr register according to the correspond ix register
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// EAX = g_dsp.r[reg]
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// ECX = g_dsp.r[DSP_REG_IX0 + reg]
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// EDX = g_dsp.r[DSP_REG_WR0 + reg]
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// EDI = tomask(EDX)
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// EAX = g_dsp.r.ar[reg]
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// EDX = g_dsp.r.wr[reg]
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// ESI = g_dsp.r.ix[reg]
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// ECX = temp
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// EDI = temp
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void DSPEmitter::decrease_addr_reg(int reg)
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{
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/*
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u16 ar = g_dsp.r[reg];
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u16 wr = g_dsp.r[reg+8];
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u16 ix = g_dsp.r[reg+4];
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u16 m = ToMask(wr) | 1;
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u16 nar = ar-ix; //!!
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if ((u16)ix > 0x8000) { // equiv: ix < 0 && ix != -0x8000 //!!
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if((ar&m) - (int)(ix&m) >= 0) //!!
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nar -= wr+1;
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} else {
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if((ar&m) - (int)(ix&m) < m-wr) //!!
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nar += wr+1;
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}
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return nar;
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*/
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#ifdef _M_IX86 // All32
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MOV(16, R(SI), M(&g_dsp.r.ix[reg]));
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MOV(16, R(AX), M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EAX, M(&g_dsp.r.ar[reg]));
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MOVZX(32, 16, EDX, M(&g_dsp.r.wr[reg]));
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MOVSX(32, 16, ESI, M(&g_dsp.r.ix[reg]));
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#else
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// MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOV(16, R(SI), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
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||||
MOV(16, R(AX), MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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||||
MOVZX(32, 16, EAX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])));
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||||
MOVZX(32, 16, EDX, MDisp(R11, STRUCT_OFFSET(g_dsp.r, wr[reg])));
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||||
MOVSX(32, 16, ESI, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ix[reg])));
|
||||
#endif
|
||||
|
||||
// ToMask(WR0), calculating it into EDI
|
||||
//u16 m = ToMask(wr) | 1;
|
||||
MOV(32, R(EDI), R(EDX));
|
||||
ToMask(DI);
|
||||
NOT(32, R(ESI)); //esi = ~ix
|
||||
|
||||
//u16 nar = ar-ix;
|
||||
MOV(16, R(CX), R(AX));
|
||||
SUB(16, R(AX), R(SI));
|
||||
//u32 nar = ar - ix; (ar + ~ix + 1)
|
||||
LEA(32, EDI, MComplex(EAX, ESI, 1, 1));
|
||||
|
||||
CMP(16, R(SI), Imm16(0x8000));
|
||||
FixupBranch negative = J_CC(CC_BE);
|
||||
//u32 dar = (nar ^ ar ^ ~ix) & ((wr | 1) << 1);
|
||||
//eax = dar
|
||||
XOR(32, R(EAX), R(ESI));
|
||||
XOR(32, R(EAX), R(EDI));
|
||||
LEA(32, ECX, MComplex(EDX, EDX, 1, 0));
|
||||
OR(32, R(ECX), Imm8(2));
|
||||
AND(32, R(EAX), R(ECX));
|
||||
|
||||
//(ar&m) + (ix&m)
|
||||
AND(32, R(ECX), R(EDI));
|
||||
AND(32, R(ESI), R(EDI));
|
||||
SUB(32, R(ECX), R(ESI));
|
||||
//if ((u32)ix > 0xFFFF8000) ==> (~ix < 0x00007FFF)
|
||||
CMP(32, R(ESI), Imm32(0x00007FFF));
|
||||
FixupBranch positive = J_CC(CC_AE);
|
||||
//if (dar > wr)
|
||||
CMP(32, R(EAX), R(EDX));
|
||||
FixupBranch done = J_CC(CC_BE);
|
||||
//nar -= wr + 1;
|
||||
SUB(16, R(DI), R(DX));
|
||||
SUB(16, R(DI), Imm8(1));
|
||||
FixupBranch done2 = J();
|
||||
|
||||
CMP(32, R(ECX), Imm32(0));
|
||||
FixupBranch out1 = J_CC(CC_L);
|
||||
SUB(16, R(AX), R(DX));
|
||||
SUB(16, R(AX), Imm16(1));
|
||||
FixupBranch out2 = J();
|
||||
//else
|
||||
SetJumpTarget(positive);
|
||||
//if ((((nar + wr + 1) ^ nar) & dar) <= wr)
|
||||
LEA(32, ECX, MComplex(EDI, EDX, 1, 1));
|
||||
XOR(32, R(ECX), R(EDI));
|
||||
AND(32, R(ECX), R(EAX));
|
||||
CMP(32, R(ECX), R(EDX));
|
||||
FixupBranch done3 = J_CC(CC_A);
|
||||
//nar += wr + 1;
|
||||
LEA(16, DI, MComplex(DI, DX, 1, 1));
|
||||
|
||||
SetJumpTarget(negative);
|
||||
SetJumpTarget(done);
|
||||
SetJumpTarget(done2);
|
||||
SetJumpTarget(done3);
|
||||
//return nar
|
||||
|
||||
//(ar&m) + (ix&m)
|
||||
AND(32, R(ECX), R(EDI));
|
||||
AND(32, R(ESI), R(EDI));
|
||||
SUB(32, R(ECX), R(ESI));
|
||||
|
||||
//m-wr
|
||||
SUB(32, R(EDI), R(EDX));
|
||||
CMP(32, R(ECX), R(EDI));
|
||||
FixupBranch out3 = J_CC(CC_GE);
|
||||
ADD(16, R(AX), R(DX));
|
||||
ADD(16, R(AX), Imm16(1));
|
||||
|
||||
SetJumpTarget(out1);
|
||||
SetJumpTarget(out2);
|
||||
SetJumpTarget(out3);
|
||||
|
||||
// g_dsp.r[reg] = tmp;
|
||||
#ifdef _M_IX86 // All32
|
||||
MOV(16, M(&g_dsp.r.ar[reg]), R(EAX));
|
||||
MOV(16, M(&g_dsp.r.ar[reg]), R(DI));
|
||||
#else
|
||||
// MOV(64, R(R11), ImmPtr(&g_dsp.r));
|
||||
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(EAX));
|
||||
MOV(16, MDisp(R11, STRUCT_OFFSET(g_dsp.r, ar[reg])), R(DI));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue