ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #9464 from Sintendo/jit64addxreloaded 

Jit64: addx revisited
This commit is contained in:
JosJuice 2021-06-28 13:53:44 +02:00 committed by GitHub
parent 156f625106 6a51c1564f
commit 2ef2eee2e0
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 43 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
View File

@ -1665,6 +1665,47 @@ void Jit64::addx(UGeckoInstruction inst)
if (inst.OE) if (inst.OE)
GenerateConstantOverflow((s64)i + (s64)j); GenerateConstantOverflow((s64)i + (s64)j);
} }
else if (gpr.IsImm(a) || gpr.IsImm(b))
{
auto [i, j] = gpr.IsImm(a) ? std::pair(a, b) : std::pair(b, a);
s32 imm = gpr.SImm32(i);
RCOpArg Rj = gpr.Use(j, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Rj, Rd);
if (imm == 0)
{
if (d != j)
MOV(32, Rd, Rj);
if (inst.OE)
GenerateConstantOverflow(false);
}
else if (d == j)
{
ADD(32, Rd, Imm32(imm));
if (inst.OE)
GenerateOverflow();
}
else if (Rj.IsSimpleReg() && !inst.OE)
{
LEA(32, Rd, MDisp(Rj.GetSimpleReg(), imm));
}
else if (imm >= -128 && imm <= 127)
{
MOV(32, Rd, Rj);
ADD(32, Rd, Imm32(imm));
if (inst.OE)
GenerateOverflow();
}
else
{
MOV(32, Rd, Imm32(imm));
ADD(32, Rd, Rj);
if (inst.OE)
GenerateOverflow();
}
}
else else
{ {
RCOpArg Ra = gpr.Use(a, RCMode::Read); RCOpArg Ra = gpr.Use(a, RCMode::Read);
@ -1672,52 +1713,15 @@ void Jit64::addx(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write); RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd); RegCache::Realize(Ra, Rb, Rd);
if ((d == a) || (d == b)) if (d == a || d == b)
{ {
RCOpArg& Rnotd = (d == a) ? Rb : Ra; RCOpArg& Rnotd = (d == a) ? Rb : Ra;
if (!Rnotd.IsZero() || inst.OE) ADD(32, Rd, Rnotd);
{
ADD(32, Rd, Rnotd);
}
} }
else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE) else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
{ {
LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg())); LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
} }
else if ((Ra.IsSimpleReg() || Rb.IsSimpleReg()) && (Ra.IsImm() || Rb.IsImm()) && !inst.OE)
{
RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
RCOpArg& Rreg = Ra.IsImm() ? Rb : Ra;
if (Rimm.IsZero())
{
MOV(32, Rd, Rreg);
}
else
{
LEA(32, Rd, MDisp(Rreg.GetSimpleReg(), Rimm.SImm32()));
}
}
else if (Ra.IsImm() || Rb.IsImm())
{
RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
RCOpArg& Rother = Ra.IsImm() ? Rb : Ra;
s32 imm = Rimm.SImm32();
if (imm >= -128 && imm <= 127)
{
MOV(32, Rd, Rother);
if (imm != 0 || inst.OE)
{
ADD(32, Rd, Rimm);
}
}
else
{
MOV(32, Rd, Rimm);
ADD(32, Rd, Rother);
}
}
else else
{ {
MOV(32, Rd, Ra); MOV(32, Rd, Ra);