JitArm64: Use BitSet8 for Arm64GPRCache::FlushCRRegisters
There are only 8 CR registers, after all.
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@ -280,7 +280,7 @@ void Arm64GPRCache::FlushRegisters(BitSet32 regs, bool maintain_state, ARM64Reg
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}
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}
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}
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void Arm64GPRCache::FlushCRRegisters(BitSet32 regs, bool maintain_state, ARM64Reg tmp_reg)
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void Arm64GPRCache::FlushCRRegisters(BitSet8 regs, bool maintain_state, ARM64Reg tmp_reg)
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{
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{
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for (size_t i = 0; i < GUEST_CR_COUNT; ++i)
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for (size_t i = 0; i < GUEST_CR_COUNT; ++i)
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{
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{
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@ -296,8 +296,8 @@ void Arm64GPRCache::FlushCRRegisters(BitSet32 regs, bool maintain_state, ARM64Re
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void Arm64GPRCache::Flush(FlushMode mode, ARM64Reg tmp_reg)
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void Arm64GPRCache::Flush(FlushMode mode, ARM64Reg tmp_reg)
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{
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{
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FlushRegisters(BitSet32(~0U), mode == FlushMode::MaintainState, tmp_reg);
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FlushRegisters(BitSet32(0xFFFFFFFF), mode == FlushMode::MaintainState, tmp_reg);
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FlushCRRegisters(BitSet32(~0U), mode == FlushMode::MaintainState, tmp_reg);
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FlushCRRegisters(BitSet8(0xFF), mode == FlushMode::MaintainState, tmp_reg);
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}
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}
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ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg)
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ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg)
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@ -330,7 +330,7 @@ public:
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FlushRegisters(regs, false, tmp_reg);
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FlushRegisters(regs, false, tmp_reg);
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}
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}
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void StoreCRRegisters(BitSet32 regs, Arm64Gen::ARM64Reg tmp_reg = Arm64Gen::ARM64Reg::INVALID_REG)
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void StoreCRRegisters(BitSet8 regs, Arm64Gen::ARM64Reg tmp_reg = Arm64Gen::ARM64Reg::INVALID_REG)
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{
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{
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FlushCRRegisters(regs, false, tmp_reg);
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FlushCRRegisters(regs, false, tmp_reg);
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}
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}
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@ -365,7 +365,7 @@ private:
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void BindToRegister(const GuestRegInfo& guest_reg, bool will_read, bool will_write = true);
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void BindToRegister(const GuestRegInfo& guest_reg, bool will_read, bool will_write = true);
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void FlushRegisters(BitSet32 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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void FlushRegisters(BitSet32 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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void FlushCRRegisters(BitSet32 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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void FlushCRRegisters(BitSet8 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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};
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};
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class Arm64FPRCache : public Arm64RegCache
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class Arm64FPRCache : public Arm64RegCache
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