From 2e622c17dce5ad0a6b50095deb7ba8ab51fc0cb9 Mon Sep 17 00:00:00 2001 From: nakeee Date: Wed, 24 Mar 2010 05:05:25 +0000 Subject: [PATCH] Remove the UDSP union functions are passed by value rather than by reference This is part of a bigger change so please report if it broke compile git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5228 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/DSPCore/Src/DSPAnalyzer.cpp | 4 +- Source/Core/DSPCore/Src/DSPIntExtOps.cpp | 124 +++--- Source/Core/DSPCore/Src/DSPIntExtOps.h | 42 +- Source/Core/DSPCore/Src/DSPInterpreter.h | 240 +++++------ Source/Core/DSPCore/Src/DSPTables.cpp | 423 +++++++++---------- Source/Core/DSPCore/Src/DSPTables.h | 22 +- Source/Core/DSPCore/Src/DspIntArithmetic.cpp | 248 +++++------ Source/Core/DSPCore/Src/DspIntBranch.cpp | 48 +-- Source/Core/DSPCore/Src/DspIntLoadStore.cpp | 97 ++--- Source/Core/DSPCore/Src/DspIntMisc.cpp | 52 +-- Source/Core/DSPCore/Src/DspIntMultiplier.cpp | 138 +++--- Source/Core/DSPCore/Src/disassemble.cpp | 2 +- 12 files changed, 721 insertions(+), 719 deletions(-) diff --git a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp index 80b86d728c..740002ba75 100644 --- a/Source/Core/DSPCore/Src/DSPAnalyzer.cpp +++ b/Source/Core/DSPCore/Src/DSPAnalyzer.cpp @@ -91,12 +91,12 @@ void AnalyzeRange(int start_addr, int end_addr) } code_flags[addr] |= CODE_START_OF_INST; // Look for loops. (this is not used atm) - if ((inst.hex & 0xffe0) == 0x0060 || (inst.hex & 0xff00) == 0x1100) { + if ((inst & 0xffe0) == 0x0060 || (inst & 0xff00) == 0x1100) { // BLOOP, BLOOPI u16 loop_end = dsp_imem_read(addr + 1); code_flags[addr] |= CODE_LOOP_START; code_flags[loop_end] |= CODE_LOOP_END; - } else if ((inst.hex & 0xffe0) == 0x0040 || (inst.hex & 0xff00) == 0x1000) { + } else if ((inst & 0xffe0) == 0x0040 || (inst & 0xff00) == 0x1000) { // LOOP, LOOPI code_flags[addr] |= CODE_LOOP_START; code_flags[addr + 1] |= CODE_LOOP_END; diff --git a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp index 332f5c20d0..73527a1ba2 100644 --- a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp +++ b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp @@ -54,22 +54,22 @@ inline bool IsSameMemArea(u16 a, u16 b) // DR $arR // xxxx xxxx 0000 01rr // Decrement addressing register $arR. -void dr(const UDSPInstruction& opc) { - writeToBackLog(0, opc.hex & 0x3, dsp_decrement_addr_reg(opc.hex & 0x3)); +void dr(const UDSPInstruction opc) { + writeToBackLog(0, opc & 0x3, dsp_decrement_addr_reg(opc & 0x3)); } // IR $arR // xxxx xxxx 0000 10rr // Increment addressing register $arR. -void ir(const UDSPInstruction& opc) { - writeToBackLog(0, opc.hex & 0x3, dsp_increment_addr_reg(opc.hex & 0x3)); +void ir(const UDSPInstruction opc) { + writeToBackLog(0, opc & 0x3, dsp_increment_addr_reg(opc & 0x3)); } // NR $arR // xxxx xxxx 0000 11rr // Add corresponding indexing register $ixR to addressing register $arR. -void nr(const UDSPInstruction& opc) { - u8 reg = opc.hex & 0x3; +void nr(const UDSPInstruction opc) { + u8 reg = opc & 0x3; writeToBackLog(0, reg, dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg])); } @@ -77,10 +77,10 @@ void nr(const UDSPInstruction& opc) { // MV $axD.D, $acS.S // xxxx xxxx 0001 ddss // Move value of $acS.S to the $axD.D. -void mv(const UDSPInstruction& opc) +void mv(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x3) + DSP_REG_ACL0; - u8 dreg = ((opc.hex >> 2) & 0x3); + u8 sreg = (opc & 0x3) + DSP_REG_ACL0; + u8 dreg = ((opc >> 2) & 0x3); #if 0 //more tests if ((sreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) @@ -94,10 +94,10 @@ void mv(const UDSPInstruction& opc) // xxxx xxxx 001s s0dd // Store value of $acS.S in the memory pointed by register $arD. // Post increment register $arD. -void s(const UDSPInstruction& opc) +void s(const UDSPInstruction opc) { - u8 dreg = opc.hex & 0x3; - u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACL0; + u8 dreg = opc & 0x3; + u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0; dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]); writeToBackLog(0, dreg, dsp_increment_addr_reg(dreg)); @@ -107,10 +107,10 @@ void s(const UDSPInstruction& opc) // xxxx xxxx 001s s1dd // Store value of register $acS.S in the memory pointed by register $arD. // Add indexing register $ixD to register $arD. -void sn(const UDSPInstruction& opc) +void sn(const UDSPInstruction opc) { - u8 dreg = opc.hex & 0x3; - u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACL0; + u8 dreg = opc & 0x3; + u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0; dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]); writeToBackLog(0, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg])); @@ -120,10 +120,10 @@ void sn(const UDSPInstruction& opc) // xxxx xxxx 01dd d0ss // Load $axD.D/$acD.D with value from memory pointed by register $arS. // Post increment register $arS. -void l(const UDSPInstruction& opc) +void l(const UDSPInstruction opc) { - u8 sreg = opc.hex & 0x3; - u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0; + u8 sreg = opc & 0x3; + u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0; if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) { @@ -144,10 +144,10 @@ void l(const UDSPInstruction& opc) // xxxx xxxx 01dd d0ss // Load $axD.D/$acD.D with value from memory pointed by register $arS. // Add indexing register register $ixS to register $arS. -void ln(const UDSPInstruction& opc) +void ln(const UDSPInstruction opc) { - u8 sreg = opc.hex & 0x3; - u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0; + u8 sreg = opc & 0x3; + u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0; if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) { @@ -169,10 +169,10 @@ void ln(const UDSPInstruction& opc) // Load register $axD.D with value from memory pointed by register // $ar0. Store value from register $acS.m to memory location pointed by // register $ar3. Increment both $ar0 and $ar3. -void ls(const UDSPInstruction& opc) +void ls(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]); @@ -188,10 +188,10 @@ void ls(const UDSPInstruction& opc) // $ar0. Store value from register $acS.m to memory location pointed by // register $ar3. Add corresponding indexing register $ix0 to addressing // register $ar0 and increment $ar3. -void lsn(const UDSPInstruction& opc) +void lsn(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]); @@ -206,10 +206,10 @@ void lsn(const UDSPInstruction& opc) // $ar0. Store value from register $acS.m to memory location pointed by // register $ar3. Add corresponding indexing register $ix3 to addressing // register $ar3 and increment $ar0. -void lsm(const UDSPInstruction& opc) +void lsm(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]); @@ -225,10 +225,10 @@ void lsm(const UDSPInstruction& opc) // register $ar3. Add corresponding indexing register $ix0 to addressing // register $ar0 and add corresponding indexing register $ix3 to addressing // register $ar3. -void lsnm(const UDSPInstruction& opc) +void lsnm(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]); @@ -242,10 +242,10 @@ void lsnm(const UDSPInstruction& opc) // Store value from register $acS.m to memory location pointed by register // $ar0. Load register $axD.D with value from memory pointed by register // $ar3. Increment both $ar0 and $ar3. -void sl(const UDSPInstruction& opc) +void sl(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]); @@ -260,10 +260,10 @@ void sl(const UDSPInstruction& opc) // $ar0. Load register $axD.D with value from memory pointed by register // $ar3. Add corresponding indexing register $ix0 to addressing register $ar0 // and increment $ar3. -void sln(const UDSPInstruction& opc) +void sln(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]); @@ -278,10 +278,10 @@ void sln(const UDSPInstruction& opc) // $ar0. Load register $axD.D with value from memory pointed by register // $ar3. Add corresponding indexing register $ix3 to addressing register $ar3 // and increment $ar0. -void slm(const UDSPInstruction& opc) +void slm(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]); @@ -296,10 +296,10 @@ void slm(const UDSPInstruction& opc) // $ar0. Load register $axD.D with value from memory pointed by register // $ar3. Add corresponding indexing register $ix0 to addressing register $ar0 // and add corresponding indexing register $ix3 to addressing register $ar3. -void slnm(const UDSPInstruction& opc) +void slnm(const UDSPInstruction opc) { - u8 sreg = (opc.hex & 0x1) + DSP_REG_ACM0; - u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0; + u8 sreg = (opc & 0x1) + DSP_REG_ACM0; + u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0; dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]); @@ -317,11 +317,11 @@ void slnm(const UDSPInstruction& opc) // then the value pointed by AR0 is loaded to BOTH AX0.H and AX0.L. // If AR0 points into an invalid memory page (ie 0x2000), then AX0.H keeps its old value. (not implemented yet) // If AR3 points into an invalid memory page, then AX0.L gets the same value as AX0.H. (not implemented yet) -void ld(const UDSPInstruction& opc) +void ld(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x1; - u8 rreg = (opc.hex >> 4) & 0x1; - u8 sreg = opc.hex & 0x3; + u8 dreg = (opc >> 5) & 0x1; + u8 rreg = (opc >> 4) & 0x1; + u8 sreg = opc & 0x3; if (sreg != DSP_REG_AR3) { writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg])); @@ -348,11 +348,11 @@ void ld(const UDSPInstruction& opc) // LDN $ax0.d, $ax1.r, @$arS // xxxx xxxx 11dr 01ss -void ldn(const UDSPInstruction& opc) +void ldn(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x1; - u8 rreg = (opc.hex >> 4) & 0x1; - u8 sreg = opc.hex & 0x3; + u8 dreg = (opc >> 5) & 0x1; + u8 rreg = (opc >> 4) & 0x1; + u8 sreg = opc & 0x3; if (sreg != DSP_REG_AR3) { writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg])); @@ -379,11 +379,11 @@ void ldn(const UDSPInstruction& opc) // LDM $ax0.d, $ax1.r, @$arS // xxxx xxxx 11dr 10ss -void ldm(const UDSPInstruction& opc) +void ldm(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x1; - u8 rreg = (opc.hex >> 4) & 0x1; - u8 sreg = opc.hex & 0x3; + u8 dreg = (opc >> 5) & 0x1; + u8 rreg = (opc >> 4) & 0x1; + u8 sreg = opc & 0x3; if (sreg != DSP_REG_AR3) { writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg])); @@ -411,11 +411,11 @@ void ldm(const UDSPInstruction& opc) // LDNM $ax0.d, $ax1.r, @$arS // xxxx xxxx 11dr 11ss -void ldnm(const UDSPInstruction& opc) +void ldnm(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x1; - u8 rreg = (opc.hex >> 4) & 0x1; - u8 sreg = opc.hex & 0x3; + u8 dreg = (opc >> 5) & 0x1; + u8 rreg = (opc >> 4) & 0x1; + u8 sreg = opc & 0x3; if (sreg != DSP_REG_AR3) { writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg])); @@ -442,7 +442,7 @@ void ldnm(const UDSPInstruction& opc) } -void nop(const UDSPInstruction& opc) +void nop(const UDSPInstruction opc) { } diff --git a/Source/Core/DSPCore/Src/DSPIntExtOps.h b/Source/Core/DSPCore/Src/DSPIntExtOps.h index 9f6b713f90..c154af24ee 100644 --- a/Source/Core/DSPCore/Src/DSPIntExtOps.h +++ b/Source/Core/DSPCore/Src/DSPIntExtOps.h @@ -36,27 +36,27 @@ namespace DSPInterpreter { namespace Ext { -void l(const UDSPInstruction& opc); -void ln(const UDSPInstruction& opc); -void ls(const UDSPInstruction& opc); -void lsn(const UDSPInstruction& opc); -void lsm(const UDSPInstruction& opc); -void lsnm(const UDSPInstruction& opc); -void sl(const UDSPInstruction& opc); -void sln(const UDSPInstruction& opc); -void slm(const UDSPInstruction& opc); -void slnm(const UDSPInstruction& opc); -void s(const UDSPInstruction& opc); -void sn(const UDSPInstruction& opc); -void ld(const UDSPInstruction& opc); -void ldn(const UDSPInstruction& opc); -void ldm(const UDSPInstruction& opc); -void ldnm(const UDSPInstruction& opc); -void mv(const UDSPInstruction& opc); -void dr(const UDSPInstruction& opc); -void ir(const UDSPInstruction& opc); -void nr(const UDSPInstruction& opc); -void nop(const UDSPInstruction& opc); +void l(const UDSPInstruction opc); +void ln(const UDSPInstruction opc); +void ls(const UDSPInstruction opc); +void lsn(const UDSPInstruction opc); +void lsm(const UDSPInstruction opc); +void lsnm(const UDSPInstruction opc); +void sl(const UDSPInstruction opc); +void sln(const UDSPInstruction opc); +void slm(const UDSPInstruction opc); +void slnm(const UDSPInstruction opc); +void s(const UDSPInstruction opc); +void sn(const UDSPInstruction opc); +void ld(const UDSPInstruction opc); +void ldn(const UDSPInstruction opc); +void ldm(const UDSPInstruction opc); +void ldnm(const UDSPInstruction opc); +void mv(const UDSPInstruction opc); +void dr(const UDSPInstruction opc); +void ir(const UDSPInstruction opc); +void nr(const UDSPInstruction opc); +void nop(const UDSPInstruction opc); } // end namespace Ext } // end namespace DSPinterpeter diff --git a/Source/Core/DSPCore/Src/DSPInterpreter.h b/Source/Core/DSPCore/Src/DSPInterpreter.h index ac99394b35..35db43f5f2 100644 --- a/Source/Core/DSPCore/Src/DSPInterpreter.h +++ b/Source/Core/DSPCore/Src/DSPInterpreter.h @@ -42,128 +42,128 @@ void WriteCR(u16 val); u16 ReadCR(); -typedef void (*DSPInterpreterFunc)(const UDSPInstruction& opc); +typedef void (*DSPInterpreterFunc)(const UDSPInstruction opc); // All the opcode functions. -void unknown(const UDSPInstruction& opc); -void call(const UDSPInstruction& opc); -void callr(const UDSPInstruction& opc); -void ifcc(const UDSPInstruction& opc); -void jcc(const UDSPInstruction& opc); -void jmprcc(const UDSPInstruction& opc); -void ret(const UDSPInstruction& opc); -void halt(const UDSPInstruction& opc); -void loop(const UDSPInstruction& opc); -void loopi(const UDSPInstruction& opc); -void bloop(const UDSPInstruction& opc); -void bloopi(const UDSPInstruction& opc); -void mrr(const UDSPInstruction& opc); -void lrr(const UDSPInstruction& opc); -void lrrd(const UDSPInstruction& opc); -void lrri(const UDSPInstruction& opc); -void lrrn(const UDSPInstruction& opc); -void srr(const UDSPInstruction& opc); -void srrd(const UDSPInstruction& opc); -void srri(const UDSPInstruction& opc); -void srrn(const UDSPInstruction& opc); -void lri(const UDSPInstruction& opc); -void lris(const UDSPInstruction& opc); -void lr(const UDSPInstruction& opc); -void sr(const UDSPInstruction& opc); -void si(const UDSPInstruction& opc); -void tstaxh(const UDSPInstruction& opc); -void clr(const UDSPInstruction& opc); -void clrl(const UDSPInstruction& opc); -void clrp(const UDSPInstruction& opc); -void mulc(const UDSPInstruction& opc); -void cmpar(const UDSPInstruction& opc); -void cmp(const UDSPInstruction& opc); -void tst(const UDSPInstruction& opc); -void addaxl(const UDSPInstruction& opc); -void addarn(const UDSPInstruction& opc); -void mulcac(const UDSPInstruction& opc); -void movr(const UDSPInstruction& opc); -void movax(const UDSPInstruction& opc); -void xorr(const UDSPInstruction& opc); -void andr(const UDSPInstruction& opc); -void orr(const UDSPInstruction& opc); -void andc(const UDSPInstruction& opc); -void orc(const UDSPInstruction& opc); -void xorc(const UDSPInstruction& opc); -void notc(const UDSPInstruction& opc); -void lsrnrx(const UDSPInstruction& opc); -void asrnrx(const UDSPInstruction& opc); -void lsrnr(const UDSPInstruction& opc); -void asrnr(const UDSPInstruction& opc); -void add(const UDSPInstruction& opc); -void addp(const UDSPInstruction& opc); -void cmpis(const UDSPInstruction& opc); -void addpaxz(const UDSPInstruction& opc); -void movpz(const UDSPInstruction& opc); -void decm(const UDSPInstruction& opc); -void dec(const UDSPInstruction& opc); -void inc(const UDSPInstruction& opc); -void incm(const UDSPInstruction& opc); -void neg(const UDSPInstruction& opc); -void addax(const UDSPInstruction& opc); -void addr(const UDSPInstruction& opc); -void subr(const UDSPInstruction& opc); -void subp(const UDSPInstruction& opc); -void subax(const UDSPInstruction& opc); -void addis(const UDSPInstruction& opc); -void addi(const UDSPInstruction& opc); -void lsl16(const UDSPInstruction& opc); -void madd(const UDSPInstruction& opc); -void msub(const UDSPInstruction& opc); -void lsr16(const UDSPInstruction& opc); -void asr16(const UDSPInstruction& opc); -void lsl(const UDSPInstruction& opc); -void lsr(const UDSPInstruction& opc); -void asl(const UDSPInstruction& opc); -void asr(const UDSPInstruction& opc); -void lsrn(const UDSPInstruction& opc); -void asrn(const UDSPInstruction& opc); -void dar(const UDSPInstruction& opc); -void iar(const UDSPInstruction& opc); -void subarn(const UDSPInstruction& opc); -void sbclr(const UDSPInstruction& opc); -void sbset(const UDSPInstruction& opc); -void mov(const UDSPInstruction& opc); -void movp(const UDSPInstruction& opc); -void mul(const UDSPInstruction& opc); -void mulac(const UDSPInstruction& opc); -void mulmv(const UDSPInstruction& opc); -void mulmvz(const UDSPInstruction& opc); -void mulx(const UDSPInstruction& opc); -void mulxac(const UDSPInstruction& opc); -void mulxmv(const UDSPInstruction& opc); -void mulxmvz(const UDSPInstruction& opc); -void mulcmvz(const UDSPInstruction& opc); -void mulcmv(const UDSPInstruction& opc); -void movnp(const UDSPInstruction& opc); -void sub(const UDSPInstruction& opc); -void maddx(const UDSPInstruction& opc); -void msubx(const UDSPInstruction& opc); -void maddc(const UDSPInstruction& opc); -void msubc(const UDSPInstruction& opc); -void srs(const UDSPInstruction& opc); -void lrs(const UDSPInstruction& opc); -void nx(const UDSPInstruction& opc); -void cmpi(const UDSPInstruction& opc); -void rti(const UDSPInstruction& opc); -void ilrr(const UDSPInstruction& opc); -void ilrrd(const UDSPInstruction& opc); -void ilrri(const UDSPInstruction& opc); -void ilrrn(const UDSPInstruction& opc); -void andcf(const UDSPInstruction& opc); -void andf(const UDSPInstruction& opc); -void xori(const UDSPInstruction& opc); -void andi(const UDSPInstruction& opc); -void ori(const UDSPInstruction& opc); -void srbith(const UDSPInstruction& opc); -void mulaxh(const UDSPInstruction& opc); -void tstprod(const UDSPInstruction& opc); -void abs(const UDSPInstruction& opc); +void unknown(const UDSPInstruction opc); +void call(const UDSPInstruction opc); +void callr(const UDSPInstruction opc); +void ifcc(const UDSPInstruction opc); +void jcc(const UDSPInstruction opc); +void jmprcc(const UDSPInstruction opc); +void ret(const UDSPInstruction opc); +void halt(const UDSPInstruction opc); +void loop(const UDSPInstruction opc); +void loopi(const UDSPInstruction opc); +void bloop(const UDSPInstruction opc); +void bloopi(const UDSPInstruction opc); +void mrr(const UDSPInstruction opc); +void lrr(const UDSPInstruction opc); +void lrrd(const UDSPInstruction opc); +void lrri(const UDSPInstruction opc); +void lrrn(const UDSPInstruction opc); +void srr(const UDSPInstruction opc); +void srrd(const UDSPInstruction opc); +void srri(const UDSPInstruction opc); +void srrn(const UDSPInstruction opc); +void lri(const UDSPInstruction opc); +void lris(const UDSPInstruction opc); +void lr(const UDSPInstruction opc); +void sr(const UDSPInstruction opc); +void si(const UDSPInstruction opc); +void tstaxh(const UDSPInstruction opc); +void clr(const UDSPInstruction opc); +void clrl(const UDSPInstruction opc); +void clrp(const UDSPInstruction opc); +void mulc(const UDSPInstruction opc); +void cmpar(const UDSPInstruction opc); +void cmp(const UDSPInstruction opc); +void tst(const UDSPInstruction opc); +void addaxl(const UDSPInstruction opc); +void addarn(const UDSPInstruction opc); +void mulcac(const UDSPInstruction opc); +void movr(const UDSPInstruction opc); +void movax(const UDSPInstruction opc); +void xorr(const UDSPInstruction opc); +void andr(const UDSPInstruction opc); +void orr(const UDSPInstruction opc); +void andc(const UDSPInstruction opc); +void orc(const UDSPInstruction opc); +void xorc(const UDSPInstruction opc); +void notc(const UDSPInstruction opc); +void lsrnrx(const UDSPInstruction opc); +void asrnrx(const UDSPInstruction opc); +void lsrnr(const UDSPInstruction opc); +void asrnr(const UDSPInstruction opc); +void add(const UDSPInstruction opc); +void addp(const UDSPInstruction opc); +void cmpis(const UDSPInstruction opc); +void addpaxz(const UDSPInstruction opc); +void movpz(const UDSPInstruction opc); +void decm(const UDSPInstruction opc); +void dec(const UDSPInstruction opc); +void inc(const UDSPInstruction opc); +void incm(const UDSPInstruction opc); +void neg(const UDSPInstruction opc); +void addax(const UDSPInstruction opc); +void addr(const UDSPInstruction opc); +void subr(const UDSPInstruction opc); +void subp(const UDSPInstruction opc); +void subax(const UDSPInstruction opc); +void addis(const UDSPInstruction opc); +void addi(const UDSPInstruction opc); +void lsl16(const UDSPInstruction opc); +void madd(const UDSPInstruction opc); +void msub(const UDSPInstruction opc); +void lsr16(const UDSPInstruction opc); +void asr16(const UDSPInstruction opc); +void lsl(const UDSPInstruction opc); +void lsr(const UDSPInstruction opc); +void asl(const UDSPInstruction opc); +void asr(const UDSPInstruction opc); +void lsrn(const UDSPInstruction opc); +void asrn(const UDSPInstruction opc); +void dar(const UDSPInstruction opc); +void iar(const UDSPInstruction opc); +void subarn(const UDSPInstruction opc); +void sbclr(const UDSPInstruction opc); +void sbset(const UDSPInstruction opc); +void mov(const UDSPInstruction opc); +void movp(const UDSPInstruction opc); +void mul(const UDSPInstruction opc); +void mulac(const UDSPInstruction opc); +void mulmv(const UDSPInstruction opc); +void mulmvz(const UDSPInstruction opc); +void mulx(const UDSPInstruction opc); +void mulxac(const UDSPInstruction opc); +void mulxmv(const UDSPInstruction opc); +void mulxmvz(const UDSPInstruction opc); +void mulcmvz(const UDSPInstruction opc); +void mulcmv(const UDSPInstruction opc); +void movnp(const UDSPInstruction opc); +void sub(const UDSPInstruction opc); +void maddx(const UDSPInstruction opc); +void msubx(const UDSPInstruction opc); +void maddc(const UDSPInstruction opc); +void msubc(const UDSPInstruction opc); +void srs(const UDSPInstruction opc); +void lrs(const UDSPInstruction opc); +void nx(const UDSPInstruction opc); +void cmpi(const UDSPInstruction opc); +void rti(const UDSPInstruction opc); +void ilrr(const UDSPInstruction opc); +void ilrrd(const UDSPInstruction opc); +void ilrri(const UDSPInstruction opc); +void ilrrn(const UDSPInstruction opc); +void andcf(const UDSPInstruction opc); +void andf(const UDSPInstruction opc); +void xori(const UDSPInstruction opc); +void andi(const UDSPInstruction opc); +void ori(const UDSPInstruction opc); +void srbith(const UDSPInstruction opc); +void mulaxh(const UDSPInstruction opc); +void tstprod(const UDSPInstruction opc); +void abs(const UDSPInstruction opc); } // namespace diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp index 7b5326a3f3..e8edbd6db0 100644 --- a/Source/Core/DSPCore/Src/DSPTables.cpp +++ b/Source/Core/DSPCore/Src/DSPTables.cpp @@ -21,286 +21,285 @@ #include "DSPTables.h" #include "DSPInterpreter.h" -#include "DSPJit.h" #include "DSPIntExtOps.h" -void nop(const UDSPInstruction& opc) +void nop(const UDSPInstruction opc) { // The real nop is 0. Anything else is bad. - if (opc.hex ) + if (opc) DSPInterpreter::unknown(opc); } const DSPOPCTemplate opcodes[] = { - {"NOP", 0x0000, 0xfffc, nop, nop, 1, 0, {}, false}, + {"NOP", 0x0000, 0xfffc, nop, nop, 1, 0, {}, false, false}, - {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false}, + {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false}, - {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, false}, + {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, false, false}, - {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RET", 0x02df, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false}, - {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, nop, 1, 0, {}, false}, + {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RET", 0x02df, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, false, true}, + {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, nop, 1, 0, {}, false, true}, - {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, + {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, - {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, + {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, + {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false, true}, {"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, nop, 1, 0, {}, false}, // This is just nop - {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false}, + {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, + {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, - {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false}, + {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, + {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false}, - {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false}, + {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false}, + {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false}, - {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false}, - {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false}, - {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false}, - {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false}, + {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, + {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, + {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, + {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, - {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, false}, // discovered by ector! - {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, false}, // discovered by ector! + {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, false, false}, // discovered by ector! + {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, false, false}, // discovered by ector! - {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false}, - {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false}, - {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false}, + {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, + {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false}, + {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, nop, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false}, + {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, nop, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - {"SI", 0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false}, + {"SI", 0x1600, 0xff00, DSPInterpreter::si, nop, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false}, - {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false}, - {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false}, + {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, + {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, + {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, - {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, // F|RES: missing S64 - {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, - {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, - {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, - {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, + {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, // F|RES: missing S64 + {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, + {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, + {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, + {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, - {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false}, + {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, + {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false}, // Hermes doesn't list this - {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - - // load and store value pointed by indexing reg and increment; LRR/SRR variants - {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false}, - {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false}, - {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false}, - {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false}, - - {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false}, - {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false}, - {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false}, - {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false}, + {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, // Hermes doesn't list this + {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, // LOOPS - {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false}, - {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false}, - {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false}, - {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false}, + {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true}, + {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true}, + {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + + // load and store value pointed by indexing reg and increment; LRR/SRR variants + {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, + {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, + {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, + {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, + + {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, + {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, + {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, + {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, //2 - {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false}, - {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false}, + {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false}, + {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, nop, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false}, // opcodes that can be extended // extended opcodes, note size of opcode will be set to 0 //3 - main opcode defined by 9 bits, extension defined by last 7 bits!! - {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true}, - {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, - {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true}, + {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, + {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, + {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, + {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, + {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, + {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, + {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, + {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, + {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, + {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, + {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, //4 - {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, + {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, + {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, + {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, //5 - {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, + {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, + {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, + {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, //6 - {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true}, - {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true}, - {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true}, - {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, + {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, + {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, + {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, //7 - {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true}, - {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true}, - {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false}, + {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, + {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, + {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, //8 - {"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1, 0, {}, true}, - {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1, 0, {}, true}, - {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1, 0, {}, true}, - {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1, 0, {}, true}, - {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1, 0, {}, true}, - {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, - {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, - {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, - {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, - {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, - {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true}, + {"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 , 0, {}, true, false}, + {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, + {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 , 0, {}, true, false}, + {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1 , 0, {}, true, false}, + {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 , 0, {}, true, false}, + {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1 , 0, {}, true, false}, + {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 , 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false}, + {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, + {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, + {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, + {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, + {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, + {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1 , 0, {}, true, false}, //9 - {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1 , 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, + {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, + {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, //a-b - {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true}, - {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, - {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, + {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1 , 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false}, + {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, + {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, //c-d - {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true}, - {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true}, + {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1 , 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, + {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1 , 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, + {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, //e - {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, - {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true}, - {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, - {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true}, + {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false}, + {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false}, + {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false}, + {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false}, //f - {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, - {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, - {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong - {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0 - {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true}, + {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false}, + {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false}, + {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1 , 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false}, //Think the args are wrong + {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1 , 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false}, // clear acl0 + {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, }; const DSPOPCTemplate cw = - {"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false}; + {"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false}; const DSPOPCTemplate opcodes_ext[] = { - {"XXX", 0x0000, 0x00fc, DSPInterpreter::Ext::nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false}, + {"XXX", 0x0000, 0x00fc, DSPInterpreter::Ext::nop, nop, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false}, - {"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false}, - {"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false}, + {"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, + {"MV", 0x0010, 0x00f0, DSPInterpreter::Ext::mv, nop, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false}, - {"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false}, - {"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false}, + {"S", 0x0020, 0x00e4, DSPInterpreter::Ext::s, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false}, + {"SN", 0x0024, 0x00e4, DSPInterpreter::Ext::sn, nop, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false}, - {"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false}, + {"L", 0x0040, 0x00c4, DSPInterpreter::Ext::l, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"LN", 0x0044, 0x00c4, DSPInterpreter::Ext::ln, nop, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, - {"LS", 0x0080, 0x00ce, DSPInterpreter::Ext::ls, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false}, - {"SL", 0x0082, 0x00ce, DSPInterpreter::Ext::sl, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false}, - {"LSN", 0x0084, 0x00ce, DSPInterpreter::Ext::lsn, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false}, - {"SLN", 0x0086, 0x00ce, DSPInterpreter::Ext::sln, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false}, - {"LSM", 0x0088, 0x00ce, DSPInterpreter::Ext::lsm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false}, - {"SLM", 0x008a, 0x00ce, DSPInterpreter::Ext::slm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false}, - {"LSNM", 0x008c, 0x00ce, DSPInterpreter::Ext::lsnm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false}, - {"SLNM", 0x008e, 0x00ce, DSPInterpreter::Ext::slnm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false}, + {"LS", 0x0080, 0x00ce, DSPInterpreter::Ext::ls, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false}, + {"SL", 0x0082, 0x00ce, DSPInterpreter::Ext::sl, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false}, + {"LSN", 0x0084, 0x00ce, DSPInterpreter::Ext::lsn, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false}, + {"SLN", 0x0086, 0x00ce, DSPInterpreter::Ext::sln, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false}, + {"LSM", 0x0088, 0x00ce, DSPInterpreter::Ext::lsm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false}, + {"SLM", 0x008a, 0x00ce, DSPInterpreter::Ext::slm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false}, + {"LSNM", 0x008c, 0x00ce, DSPInterpreter::Ext::lsnm, nop, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false}, + {"SLNM", 0x008e, 0x00ce, DSPInterpreter::Ext::slnm, nop, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false}, - {"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false}, - {"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false}, + {"LD", 0x00c0, 0x00cc, DSPInterpreter::Ext::ld, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"LDN", 0x00c4, 0x00cc, DSPInterpreter::Ext::ldn, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"LDM", 0x00c8, 0x00cc, DSPInterpreter::Ext::ldm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"LDNM", 0x00cc, 0x00cc, DSPInterpreter::Ext::ldnm, nop, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, }; const int opcodes_size = sizeof(opcodes) / sizeof(DSPOPCTemplate); @@ -491,7 +490,7 @@ const DSPOPCTemplate *GetOpTemplate(const UDSPInstruction &inst) for (int i = 0; i < opcodes_size; i++) { u16 mask = opcodes[i].opcode_mask; - if ((mask & inst.hex) == opcodes[i].opcode) + if ((mask & inst) == opcodes[i].opcode) return &opcodes[i]; } return NULL; diff --git a/Source/Core/DSPCore/Src/DSPTables.h b/Source/Core/DSPCore/Src/DSPTables.h index 6e4fbdc6da..89984b6d88 100644 --- a/Source/Core/DSPCore/Src/DSPTables.h +++ b/Source/Core/DSPCore/Src/DSPTables.h @@ -67,7 +67,8 @@ enum partype_t #define OPTABLE_SIZE 0xffff + 1 #define EXT_OPTABLE_SIZE 0xff + 1 -union UDSPInstruction +typedef u16 UDSPInstruction; +/*/union UDSPInstruction { u16 hex; @@ -88,9 +89,9 @@ union UDSPInstruction }; // TODO: Figure out more instruction structures (add structs here) -}; + };*/ -typedef void (*dspInstFunc)(const UDSPInstruction&); +typedef void (*dspInstFunc)(const UDSPInstruction); struct param2_t { @@ -114,6 +115,7 @@ typedef struct u8 param_count; param2_t params[8]; bool extended; + bool branch; } DSPOPCTemplate; typedef DSPOPCTemplate opc_t; @@ -155,16 +157,16 @@ void applyWriteBackLog(); void zeroWriteBackLog(); void zeroWriteBackLogPreserveAcc(u8 acc); -inline void ExecuteInstruction(const UDSPInstruction& inst) +inline void ExecuteInstruction(const UDSPInstruction inst) { - if (opTableUseExt[inst.hex]) { - if ((inst.hex >> 12) == 0x3) - extOpTable[inst.hex & 0x7F](inst); + if (opTableUseExt[inst]) { + if ((inst >> 12) == 0x3) + extOpTable[inst & 0x7F](inst); else - extOpTable[inst.hex & 0xFF](inst); + extOpTable[inst & 0xFF](inst); } - opTable[inst.hex](inst); - if (opTableUseExt[inst.hex]) { + opTable[inst](inst); + if (opTableUseExt[inst]) { applyWriteBackLog(); } } diff --git a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp index 9bdaa4cefb..6396b5b96e 100644 --- a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp +++ b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp @@ -30,9 +30,9 @@ namespace DSPInterpreter { // Clears accumulator $acR // // flags out: --10 0100 -void clr(const UDSPInstruction& opc) +void clr(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 11) & 0x1; + u8 reg = (opc >> 11) & 0x1; dsp_set_long_acc(reg, 0); Update_SR_Register64(0); @@ -44,9 +44,9 @@ void clr(const UDSPInstruction& opc) // Clears $acR.l - low 16 bits of accumulator $acR. // // flags out: --xx xx00 -void clrl(const UDSPInstruction& opc) +void clrl(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; s64 acc = (dsp_get_long_acc(reg) + 0x8000) & ~0xffff; @@ -65,9 +65,9 @@ void clrl(const UDSPInstruction& opc) // accumulator mid part $acD.m with immediate value I is equal I. // // flags out: -x-- ---- -void andcf(const UDSPInstruction& opc) +void andcf(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; u16 imm = dsp_fetch_code(); u16 val = dsp_get_acc_m(reg); @@ -82,9 +82,9 @@ void andcf(const UDSPInstruction& opc) // immediate value 0. // // flags out: -x-- ---- -void andf(const UDSPInstruction& opc) +void andf(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; u16 imm = dsp_fetch_code(); u16 val = dsp_get_acc_m(reg); @@ -98,9 +98,9 @@ void andf(const UDSPInstruction& opc) // Test accumulator %acR. // // flags out: --xx xx00 -void tst(const UDSPInstruction& opc) +void tst(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 11) & 0x1; + u8 reg = (opc >> 11) & 0x1; s64 acc = dsp_get_long_acc(reg); Update_SR_Register64(acc); @@ -112,9 +112,9 @@ void tst(const UDSPInstruction& opc) // Test high part of secondary accumulator $axR.h. // // flags out: --x0 xx00 -void tstaxh(const UDSPInstruction& opc) +void tstaxh(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; s16 val = dsp_get_ax_h(reg); Update_SR_Register16(val); @@ -128,7 +128,7 @@ void tstaxh(const UDSPInstruction& opc) // Compares accumulator $ac0 with accumulator $ac1. // // flags out: x-xx xxxx -void cmp(const UDSPInstruction& opc) +void cmp(const UDSPInstruction opc) { s64 acc0 = dsp_get_long_acc(0); s64 acc1 = dsp_get_long_acc(1); @@ -144,10 +144,10 @@ void cmp(const UDSPInstruction& opc) // Not described by Duddie's doc - at least not as a separate instruction. // // flags out: x-xx xxxx -void cmpar(const UDSPInstruction& opc) +void cmpar(const UDSPInstruction opc) { - u8 rreg = ((opc.hex >> 12) & 0x1) + DSP_REG_AXH0; - u8 sreg = (opc.hex >> 11) & 0x1; + u8 rreg = ((opc >> 12) & 0x1) + DSP_REG_AXH0; + u8 sreg = (opc >> 11) & 0x1; s64 sr = dsp_get_long_acc(sreg); s64 rr = (s16)g_dsp.r[rreg]; @@ -165,9 +165,9 @@ void cmpar(const UDSPInstruction& opc) // Although flags are being set regarding whole accumulator register. // // flags out: x-xx xxxx -void cmpi(const UDSPInstruction& opc) +void cmpi(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; s64 val = dsp_get_long_acc(reg); s64 imm = (s64)(s16)dsp_fetch_code() << 16; // Immediate is considered to be at M level in the 40-bit accumulator. @@ -183,12 +183,12 @@ void cmpi(const UDSPInstruction& opc) // $acD.hm and computing flags based on whole accumulator $acD. // // flags out: x-xx xxxx -void cmpis(const UDSPInstruction& opc) +void cmpis(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 8) & 0x1; + u8 areg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(areg); - s64 val = (s8)opc.hex; + s64 val = (s8)opc; val <<= 16; s64 res = dsp_convert_long_acc(acc - val); @@ -204,10 +204,10 @@ void cmpis(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void xorr(const UDSPInstruction& opc) +void xorr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ g_dsp.r[DSP_REG_AXH0 + sreg]; zeroWriteBackLogPreserveAcc(dreg); @@ -223,10 +223,10 @@ void xorr(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void andr(const UDSPInstruction& opc) +void andr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] & g_dsp.r[DSP_REG_AXH0 + sreg]; zeroWriteBackLogPreserveAcc(dreg); @@ -242,10 +242,10 @@ void andr(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void orr(const UDSPInstruction& opc) +void orr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] | g_dsp.r[DSP_REG_AXH0 + sreg]; zeroWriteBackLogPreserveAcc(dreg); @@ -261,9 +261,9 @@ void orr(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void andc(const UDSPInstruction& opc) +void andc(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] & g_dsp.r[DSP_REG_ACM0 + (1 - dreg)]; zeroWriteBackLogPreserveAcc(dreg); @@ -279,9 +279,9 @@ void andc(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void orc(const UDSPInstruction& opc) +void orc(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] | g_dsp.r[DSP_REG_ACM0 + (1 - dreg)]; zeroWriteBackLogPreserveAcc(dreg); @@ -296,9 +296,9 @@ void orc(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void xorc(const UDSPInstruction& opc) +void xorc(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ g_dsp.r[DSP_REG_ACM0 + (1 - dreg)]; zeroWriteBackLogPreserveAcc(dreg); @@ -313,9 +313,9 @@ void xorc(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void notc(const UDSPInstruction& opc) +void notc(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u16 accm = g_dsp.r[DSP_REG_ACM0 + dreg] ^ 0xffff; zeroWriteBackLogPreserveAcc(dreg); @@ -331,9 +331,9 @@ void notc(const UDSPInstruction& opc) // immediate value I. // // flags out: --xx xx00 -void xori(const UDSPInstruction& opc) +void xori(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; u16 imm = dsp_fetch_code(); g_dsp.r[DSP_REG_ACM0 + reg] ^= imm; @@ -346,9 +346,9 @@ void xori(const UDSPInstruction& opc) // Logic AND of accumulator mid part $acD.m with immediate value I. // // flags out: --xx xx00 -void andi(const UDSPInstruction& opc) +void andi(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; u16 imm = dsp_fetch_code(); g_dsp.r[DSP_REG_ACM0 + reg] &= imm; @@ -361,9 +361,9 @@ void andi(const UDSPInstruction& opc) // Logic OR of accumulator mid part $acD.m with immediate value I. // // flags out: --xx xx00 -void ori(const UDSPInstruction& opc) +void ori(const UDSPInstruction opc) { - u8 reg = (opc.hex >> 8) & 0x1; + u8 reg = (opc >> 8) & 0x1; u16 imm = dsp_fetch_code(); g_dsp.r[DSP_REG_ACM0 + reg] |= imm; @@ -377,10 +377,10 @@ void ori(const UDSPInstruction& opc) // Adds register $axS.L to accumulator $acD.M register. // // flags out: x-xx xxxx -void addr(const UDSPInstruction& opc) +void addr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; s64 acc = dsp_get_long_acc(dreg); s64 ax = (s16)g_dsp.r[sreg]; @@ -399,10 +399,10 @@ void addr(const UDSPInstruction& opc) // Adds secondary accumulator $axS to accumulator register $acD. // // flags out: x-xx xxxx -void addax(const UDSPInstruction& opc) +void addax(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s64 acc = dsp_get_long_acc(dreg); s64 ax = dsp_get_long_acx(sreg); @@ -420,9 +420,9 @@ void addax(const UDSPInstruction& opc) // Adds accumulator $ac(1-D) to accumulator register $acD. // // flags out: x-xx xxxx -void add(const UDSPInstruction& opc) +void add(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc0 = dsp_get_long_acc(dreg); s64 acc1 = dsp_get_long_acc(1 - dreg); @@ -440,9 +440,9 @@ void add(const UDSPInstruction& opc) // Adds product register to accumulator register. // // flags out: x-xx xxxx -void addp(const UDSPInstruction& opc) +void addp(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(dreg); s64 prod = dsp_get_long_prod(); @@ -461,10 +461,10 @@ void addp(const UDSPInstruction& opc) // should be unsigned values!! // // flags out: x-xx xxxx -void addaxl(const UDSPInstruction& opc) +void addaxl(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 9) & 0x1; - u8 dreg = (opc.hex >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u64 acc = dsp_get_long_acc(dreg); u16 acx = (u16)dsp_get_ax_l(sreg); @@ -484,9 +484,9 @@ void addaxl(const UDSPInstruction& opc) // Adds immediate (16-bit sign extended) to mid accumulator $acD.hm. // // flags out: x-xx xxxx -void addi(const UDSPInstruction& opc) +void addi(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 8) & 0x1; + u8 areg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(areg); s64 imm = (s16)dsp_fetch_code(); @@ -503,12 +503,12 @@ void addi(const UDSPInstruction& opc) // Adds short immediate (8-bit sign extended) to mid accumulator $acD.hm. // // flags out: x-xx xxxx -void addis(const UDSPInstruction& opc) +void addis(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(dreg); - s64 imm = (s8)(u8)opc.hex; + s64 imm = (s8)(u8)opc; imm <<= 16; s64 res = acc + imm; @@ -522,9 +522,9 @@ void addis(const UDSPInstruction& opc) // Increment 24-bit mid-accumulator $acsD. // // flags out: x-xx xxxx -void incm(const UDSPInstruction& opc) +void incm(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 sub = 0x10000; s64 acc = dsp_get_long_acc(dreg); @@ -542,9 +542,9 @@ void incm(const UDSPInstruction& opc) // Increment accumulator $acD. // // flags out: x-xx xxxx -void inc(const UDSPInstruction& opc) +void inc(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(dreg); s64 res = acc + 1; @@ -563,10 +563,10 @@ void inc(const UDSPInstruction& opc) // Subtracts register $axS.L from accumulator $acD.M register. // // flags out: x-xx xxxx -void subr(const UDSPInstruction& opc) +void subr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; s64 acc = dsp_get_long_acc(dreg); s64 ax = (s16)g_dsp.r[sreg]; @@ -585,10 +585,10 @@ void subr(const UDSPInstruction& opc) // Subtracts secondary accumulator $axS from accumulator register $acD. // // flags out: x-xx xxxx -void subax(const UDSPInstruction& opc) +void subax(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s64 acc = dsp_get_long_acc(dreg); s64 acx = dsp_get_long_acx(sreg); @@ -606,9 +606,9 @@ void subax(const UDSPInstruction& opc) // Subtracts accumulator $ac(1-D) from accumulator register $acD. // // flags out: x-xx xxxx -void sub(const UDSPInstruction& opc) +void sub(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc1 = dsp_get_long_acc(dreg); s64 acc2 = dsp_get_long_acc(1 - dreg); @@ -626,9 +626,9 @@ void sub(const UDSPInstruction& opc) // Subtracts product register from accumulator register. // // flags out: x-xx xxxx -void subp(const UDSPInstruction& opc) +void subp(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(dreg); s64 prod = dsp_get_long_prod(); @@ -646,9 +646,9 @@ void subp(const UDSPInstruction& opc) // Decrement 24-bit mid-accumulator $acsD. // // flags out: x-xx xxxx -void decm(const UDSPInstruction& opc) +void decm(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x01; + u8 dreg = (opc >> 8) & 0x01; s64 sub = 0x10000; s64 acc = dsp_get_long_acc(dreg); @@ -666,9 +666,9 @@ void decm(const UDSPInstruction& opc) // Decrement accumulator $acD. // // flags out: x-xx xxxx -void dec(const UDSPInstruction& opc) +void dec(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x01; + u8 dreg = (opc >> 8) & 0x01; s64 acc = dsp_get_long_acc(dreg); s64 res = acc - 1; @@ -687,9 +687,9 @@ void dec(const UDSPInstruction& opc) // Negate accumulator $acD. // // flags out: --xx xx00 -void neg(const UDSPInstruction& opc) +void neg(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(dreg); acc = 0 - acc; @@ -705,9 +705,9 @@ void neg(const UDSPInstruction& opc) // absolute value of $acD // // flags out: --xx xx00 -void abs(const UDSPInstruction& opc) +void abs(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 11) & 0x1; + u8 dreg = (opc >> 11) & 0x1; s64 acc = dsp_get_long_acc(dreg); @@ -728,10 +728,10 @@ void abs(const UDSPInstruction& opc) // TODO: Check what happens to acD.h. // // flags out: --xx xx00 -void movr(const UDSPInstruction& opc) +void movr(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 8) & 0x1; - u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0; + u8 areg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 9) & 0x3) + DSP_REG_AXL0; s64 acc = (s16)g_dsp.r[sreg]; acc <<= 16; @@ -748,10 +748,10 @@ void movr(const UDSPInstruction& opc) // Moves secondary accumulator $axS to accumulator $axD. // // flags out: --xx xx00 -void movax(const UDSPInstruction& opc) +void movax(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s64 acx = dsp_get_long_acx(sreg); @@ -766,9 +766,9 @@ void movax(const UDSPInstruction& opc) // Moves accumulator $ax(1-D) to accumulator $axD. // // flags out: --x0 xx00 -void mov(const UDSPInstruction& opc) +void mov(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; u64 acc = dsp_get_long_acc(1 - dreg); zeroWriteBackLog(); @@ -784,9 +784,9 @@ void mov(const UDSPInstruction& opc) // Logically shifts left accumulator $acR by 16. // // flags out: --xx xx00 -void lsl16(const UDSPInstruction& opc) +void lsl16(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 8) & 0x1; + u8 areg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_acc(areg); acc <<= 16; @@ -802,9 +802,9 @@ void lsl16(const UDSPInstruction& opc) // Logically shifts right accumulator $acR by 16. // // flags out: --xx xx00 -void lsr16(const UDSPInstruction& opc) +void lsr16(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 8) & 0x1; + u8 areg = (opc >> 8) & 0x1; u64 acc = dsp_get_long_acc(areg); acc &= 0x000000FFFFFFFFFFULL; // Lop off the extraneous sign extension our 64-bit fake accum causes @@ -821,9 +821,9 @@ void lsr16(const UDSPInstruction& opc) // Arithmetically shifts right accumulator $acR by 16. // // flags out: --xx xx00 -void asr16(const UDSPInstruction& opc) +void asr16(const UDSPInstruction opc) { - u8 areg = (opc.hex >> 11) & 0x1; + u8 areg = (opc >> 11) & 0x1; s64 acc = dsp_get_long_acc(areg); acc >>= 16; @@ -839,10 +839,10 @@ void asr16(const UDSPInstruction& opc) // Logically shifts left accumulator $acR by number specified by value I. // // flags out: --xx xx00 -void lsl(const UDSPInstruction& opc) +void lsl(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x01; - u16 shift = opc.hex & 0x3f; + u8 rreg = (opc >> 8) & 0x01; + u16 shift = opc & 0x3f; u64 acc = dsp_get_long_acc(rreg); acc <<= shift; @@ -857,17 +857,17 @@ void lsl(const UDSPInstruction& opc) // calculated by negating sign extended bits 0-6. // // flags out: --xx xx00 -void lsr(const UDSPInstruction& opc) +void lsr(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x01; + u8 rreg = (opc >> 8) & 0x01; u16 shift; u64 acc = dsp_get_long_acc(rreg); acc &= 0x000000FFFFFFFFFFULL; // Lop off the extraneous sign extension our 64-bit fake accum causes - if ((opc.hex & 0x3f) == 0) + if ((opc & 0x3f) == 0) shift = 0; else - shift = 0x40 - (opc.hex & 0x3f); + shift = 0x40 - (opc & 0x3f); acc >>= shift; @@ -880,10 +880,10 @@ void lsr(const UDSPInstruction& opc) // Logically shifts left accumulator $acR by number specified by value I. // // flags out: --xx xx00 -void asl(const UDSPInstruction& opc) +void asl(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x01; - u16 shift = opc.hex & 0x3f; + u8 rreg = (opc >> 8) & 0x01; + u16 shift = opc & 0x3f; u64 acc = dsp_get_long_acc(rreg); acc <<= shift; @@ -898,15 +898,15 @@ void asl(const UDSPInstruction& opc) // value calculated by negating sign extended bits 0-6. // // flags out: --xx xx00 -void asr(const UDSPInstruction& opc) +void asr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x01; + u8 dreg = (opc >> 8) & 0x01; u16 shift; - if ((opc.hex & 0x3f) == 0) + if ((opc & 0x3f) == 0) shift = 0; else - shift = 0x40 - (opc.hex & 0x3f); + shift = 0x40 - (opc & 0x3f); // arithmetic shift s64 acc = dsp_get_long_acc(dreg); @@ -922,7 +922,7 @@ void asr(const UDSPInstruction& opc) // (if value negative, becomes left shift). // // flags out: --xx xx00 -void lsrn(const UDSPInstruction& opc) +void lsrn(const UDSPInstruction opc) { s16 shift; u16 accm = (u16)dsp_get_acc_m(1); @@ -952,7 +952,7 @@ void lsrn(const UDSPInstruction& opc) // (if value negative, becomes left shift). // // flags out: --xx xx00 -void asrn(const UDSPInstruction& opc) +void asrn(const UDSPInstruction opc) { s16 shift; u16 accm = (u16)dsp_get_acc_m(1); @@ -981,10 +981,10 @@ void asrn(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void lsrnrx(const UDSPInstruction& opc) +void lsrnrx(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s16 shift; u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg]; @@ -1016,10 +1016,10 @@ void lsrnrx(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void asrnrx(const UDSPInstruction& opc) +void asrnrx(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s16 shift; u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg]; @@ -1050,9 +1050,9 @@ void asrnrx(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void lsrnr(const UDSPInstruction& opc) +void lsrnr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s16 shift; u16 accm = (u16)dsp_get_acc_m(1 - dreg); @@ -1083,9 +1083,9 @@ void lsrnr(const UDSPInstruction& opc) // x = extension (7 bits!!) // // flags out: --xx xx00 -void asrnr(const UDSPInstruction& opc) +void asrnr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s16 shift; u16 accm = (u16)dsp_get_acc_m(1 - dreg); diff --git a/Source/Core/DSPCore/Src/DspIntBranch.cpp b/Source/Core/DSPCore/Src/DspIntBranch.cpp index 43614620fe..618c51d022 100644 --- a/Source/Core/DSPCore/Src/DspIntBranch.cpp +++ b/Source/Core/DSPCore/Src/DspIntBranch.cpp @@ -34,11 +34,11 @@ namespace DSPInterpreter { // Call function if condition cc has been met. Push program counter of // instruction following "call" to $st0. Set program counter to address // represented by value that follows this "call" instruction. -void call(const UDSPInstruction& opc) +void call(const UDSPInstruction opc) { // must be outside the if. u16 dest = dsp_fetch_code(); - if (CheckCondition(opc.hex & 0xf)) + if (CheckCondition(opc & 0xf)) { dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc); g_dsp.pc = dest; @@ -51,11 +51,11 @@ void call(const UDSPInstruction& opc) // Call function if condition cc has been met. Push program counter of // instruction following "call" to call stack $st0. Set program counter to // register $R. -void callr(const UDSPInstruction& opc) +void callr(const UDSPInstruction opc) { - if (CheckCondition(opc.hex & 0xf)) + if (CheckCondition(opc & 0xf)) { - u8 reg = (opc.hex >> 5) & 0x7; + u8 reg = (opc >> 5) & 0x7; u16 addr = dsp_op_read_reg(reg); dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc); g_dsp.pc = addr; @@ -66,9 +66,9 @@ void callr(const UDSPInstruction& opc) // IFcc // 0000 0010 0111 cccc // Execute following opcode if the condition has been met. -void ifcc(const UDSPInstruction& opc) +void ifcc(const UDSPInstruction opc) { - if (!CheckCondition(opc.hex & 0xf)) + if (!CheckCondition(opc & 0xf)) { // skip the next opcode - we have to lookup its size. g_dsp.pc += opSize[dsp_peek_code()]; @@ -81,10 +81,10 @@ void ifcc(const UDSPInstruction& opc) // aaaa aaaa aaaa aaaa // Jump to addressA if condition cc has been met. Set program counter to // address represented by value that follows this "jmp" instruction. -void jcc(const UDSPInstruction& opc) +void jcc(const UDSPInstruction opc) { u16 dest = dsp_fetch_code(); - if (CheckCondition(opc.hex & 0xf)) + if (CheckCondition(opc & 0xf)) { g_dsp.pc = dest; } @@ -94,11 +94,11 @@ void jcc(const UDSPInstruction& opc) // JMPcc $R // 0001 0111 rrr0 cccc // Jump to address; set program counter to a value from register $R. -void jmprcc(const UDSPInstruction& opc) +void jmprcc(const UDSPInstruction opc) { - if (CheckCondition(opc.hex & 0xf)) + if (CheckCondition(opc & 0xf)) { - u8 reg = (opc.hex >> 5) & 0x7; + u8 reg = (opc >> 5) & 0x7; g_dsp.pc = dsp_op_read_reg(reg); } } @@ -108,9 +108,9 @@ void jmprcc(const UDSPInstruction& opc) // 0000 0010 1101 cccc // Return from subroutine if condition cc has been met. Pops stored PC // from call stack $st0 and sets $pc to this location. -void ret(const UDSPInstruction& opc) +void ret(const UDSPInstruction opc) { - if (CheckCondition(opc.hex & 0xf)) + if (CheckCondition(opc & 0xf)) { g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); } @@ -121,7 +121,7 @@ void ret(const UDSPInstruction& opc) // Return from exception. Pops stored status register $sr from data stack // $st1 and program counter PC from call stack $st0 and sets $pc to this // location. -void rti(const UDSPInstruction& opc) +void rti(const UDSPInstruction opc) { g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D); g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); @@ -132,7 +132,7 @@ void rti(const UDSPInstruction& opc) // HALT // 0000 0000 0020 0001 // Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR. -void halt(const UDSPInstruction& opc) +void halt(const UDSPInstruction opc) { g_dsp.cr |= 0x4; g_dsp.pc--; @@ -182,9 +182,9 @@ void HandleLoop() // then looped instruction will not get executed. // Actually, this instruction simply prepares the loop stacks for the above. // The looping hardware takes care of the rest. -void loop(const UDSPInstruction& opc) +void loop(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x1f; + u16 reg = opc & 0x1f; u16 cnt = g_dsp.r[reg]; u16 loop_pc = g_dsp.pc; @@ -204,9 +204,9 @@ void loop(const UDSPInstruction& opc) // instruction will not get executed. // Actually, this instruction simply prepares the loop stacks for the above. // The looping hardware takes care of the rest. -void loopi(const UDSPInstruction& opc) +void loopi(const UDSPInstruction opc) { - u16 cnt = opc.hex & 0xff; + u16 cnt = opc & 0xff; u16 loop_pc = g_dsp.pc; if (cnt) @@ -227,9 +227,9 @@ void loopi(const UDSPInstruction& opc) // included in loop. Counter is pushed on loop stack $st3, end of block address // is pushed on loop stack $st2 and repeat address is pushed on call stack $st0. // Up to 4 nested loops is allowed. -void bloop(const UDSPInstruction& opc) +void bloop(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x1f; + u16 reg = opc & 0x1f; u16 cnt = g_dsp.r[reg]; u16 loop_pc = dsp_fetch_code(); @@ -255,9 +255,9 @@ void bloop(const UDSPInstruction& opc) // loop. Counter is pushed on loop stack $st3, end of block address is pushed // on loop stack $st2 and repeat address is pushed on call stack $st0. Up to 4 // nested loops is allowed. -void bloopi(const UDSPInstruction& opc) +void bloopi(const UDSPInstruction opc) { - u16 cnt = opc.hex & 0xff; + u16 cnt = opc & 0xff; u16 loop_pc = dsp_fetch_code(); if (cnt) diff --git a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp index 684222a3d9..443107a6a7 100644 --- a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp +++ b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp @@ -30,10 +30,10 @@ namespace DSPInterpreter { // CR[0-7] | M. That is, the upper 8 bits of the address are the // bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate. // Note: pc+=2 in duddie's doc seems wrong -void srs(const UDSPInstruction& opc) +void srs(const UDSPInstruction opc) { - u8 reg = ((opc.hex >> 8) & 0x7) + 0x18; - u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc.hex & 0xFF); + u8 reg = ((opc >> 8) & 0x7) + 0x18; + u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF); dsp_dmem_write(addr, g_dsp.r[reg]); } @@ -42,10 +42,10 @@ void srs(const UDSPInstruction& opc) // Move value from data memory pointed by address CR[0-7] | M to register // $(0x18+D). That is, the upper 8 bits of the address are the bottom 8 bits // from CR, and the lower 8 bits are from the 8-bit immediate. -void lrs(const UDSPInstruction& opc) +void lrs(const UDSPInstruction opc) { - u8 reg = ((opc.hex >> 8) & 0x7) + 0x18; - u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc.hex & 0xFF); + u8 reg = ((opc >> 8) & 0x7) + 0x18; + u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF); g_dsp.r[reg] = dsp_dmem_read(addr); dsp_conditional_extend_accum(reg); } @@ -55,9 +55,9 @@ void lrs(const UDSPInstruction& opc) // mmmm mmmm mmmm mmmm // Move value from data memory pointed by address M to register $D. // FIXME: Perform additional operation depending on destination register. -void lr(const UDSPInstruction& opc) +void lr(const UDSPInstruction opc) { - u8 reg = opc.hex & DSP_REG_MASK; + u8 reg = opc & DSP_REG_MASK; u16 addr = dsp_fetch_code(); u16 val = dsp_dmem_read(addr); dsp_op_write_reg(reg, val); @@ -69,9 +69,9 @@ void lr(const UDSPInstruction& opc) // mmmm mmmm mmmm mmmm // Store value from register $S to a memory pointed by address M. // FIXME: Perform additional operation depending on destination register. -void sr(const UDSPInstruction& opc) +void sr(const UDSPInstruction opc) { - u8 reg = opc.hex & DSP_REG_MASK; + u8 reg = opc & DSP_REG_MASK; u16 addr = dsp_fetch_code(); u16 val = dsp_op_read_reg(reg); dsp_dmem_write(addr, val); @@ -82,9 +82,9 @@ void sr(const UDSPInstruction& opc) // iiii iiii iiii iiii // Store 16-bit immediate value I to a memory location pointed by address // M (M is 8-bit value sign extended). -void si(const UDSPInstruction& opc) +void si(const UDSPInstruction opc) { - u16 addr = (s8)opc.hex; + u16 addr = (s8)opc; u16 imm = dsp_fetch_code(); dsp_dmem_write(addr, imm); } @@ -93,10 +93,10 @@ void si(const UDSPInstruction& opc) // 0001 1000 0ssd dddd // Move value from data memory pointed by addressing register $S to register $D. // FIXME: Perform additional operation depending on destination register. -void lrr(const UDSPInstruction& opc) +void lrr(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 5) & 0x3; - u8 dreg = opc.hex & 0x1f; + u8 sreg = (opc >> 5) & 0x3; + u8 dreg = opc & 0x1f; u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); @@ -108,10 +108,10 @@ void lrr(const UDSPInstruction& opc) // Move value from data memory pointed by addressing register $S toregister $D. // Decrement register $S. // FIXME: Perform additional operation depending on destination register. -void lrrd(const UDSPInstruction& opc) +void lrrd(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 5) & 0x3; - u8 dreg = opc.hex & 0x1f; + u8 sreg = (opc >> 5) & 0x3; + u8 dreg = opc & 0x1f; u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); @@ -124,10 +124,10 @@ void lrrd(const UDSPInstruction& opc) // Move value from data memory pointed by addressing register $S to register $D. // Increment register $S. // FIXME: Perform additional operation depending on destination register. -void lrri(const UDSPInstruction& opc) +void lrri(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 5) & 0x3; - u8 dreg = opc.hex & 0x1f; + u8 sreg = (opc >> 5) & 0x3; + u8 dreg = opc & 0x1f; u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); @@ -140,10 +140,10 @@ void lrri(const UDSPInstruction& opc) // Move value from data memory pointed by addressing register $S to register $D. // Add indexing register $(0x4+S) to register $S. // FIXME: Perform additional operation depending on destination register. -void lrrn(const UDSPInstruction& opc) +void lrrn(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 5) & 0x3; - u8 dreg = opc.hex & 0x1f; + u8 sreg = (opc >> 5) & 0x3; + u8 dreg = opc & 0x1f; u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); @@ -156,10 +156,10 @@ void lrrn(const UDSPInstruction& opc) // Store value from source register $S to a memory location pointed by // addressing register $D. // FIXME: Perform additional operation depending on source register. -void srr(const UDSPInstruction& opc) +void srr(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x3; - u8 sreg = opc.hex & 0x1f; + u8 dreg = (opc >> 5) & 0x3; + u8 sreg = opc & 0x1f; u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); @@ -170,10 +170,10 @@ void srr(const UDSPInstruction& opc) // Store value from source register $S to a memory location pointed by // addressing register $D. Decrement register $D. // FIXME: Perform additional operation depending on source register. -void srrd(const UDSPInstruction& opc) +void srrd(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x3; - u8 sreg = opc.hex & 0x1f; + u8 dreg = (opc >> 5) & 0x3; + u8 sreg = opc & 0x1f; u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); @@ -185,12 +185,13 @@ void srrd(const UDSPInstruction& opc) // Store value from source register $S to a memory location pointed by // addressing register $D. Increment register $D. // FIXME: Perform additional operation depending on source register. -void srri(const UDSPInstruction& opc) +void srri(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x3; - u8 sreg = opc.hex & 0x1f; + u8 dreg = (opc >> 5) & 0x3; + u8 sreg = opc & 0x1f; u16 val = dsp_op_read_reg(sreg); + dsp_dmem_write(g_dsp.r[dreg], val); g_dsp.r[dreg] = dsp_increment_addr_reg(dreg); } @@ -200,10 +201,10 @@ void srri(const UDSPInstruction& opc) // Store value from source register $S to a memory location pointed by // addressing register $D. Add DSP_REG_IX0 register to register $D. // FIXME: Perform additional operation depending on source register. -void srrn(const UDSPInstruction& opc) +void srrn(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 5) & 0x3; - u8 sreg = opc.hex & 0x1f; + u8 dreg = (opc >> 5) & 0x3; + u8 sreg = opc & 0x1f; u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); @@ -214,10 +215,10 @@ void srrn(const UDSPInstruction& opc) // 0000 001d 0001 00ss // Move value from instruction memory pointed by addressing register // $arS to mid accumulator register $acD.m. -void ilrr(const UDSPInstruction& opc) +void ilrr(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x3; - u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1); + u16 reg = opc & 0x3; + u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1); g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); @@ -227,10 +228,10 @@ void ilrr(const UDSPInstruction& opc) // 0000 001d 0001 01ss // Move value from instruction memory pointed by addressing register // $arS to mid accumulator register $acD.m. Decrement addressing register $arS. -void ilrrd(const UDSPInstruction& opc) +void ilrrd(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x3; - u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1); + u16 reg = opc & 0x3; + u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1); g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); @@ -241,10 +242,10 @@ void ilrrd(const UDSPInstruction& opc) // 0000 001d 0001 10ss // Move value from instruction memory pointed by addressing register // $arS to mid accumulator register $acD.m. Increment addressing register $arS. -void ilrri(const UDSPInstruction& opc) +void ilrri(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x3; - u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1); + u16 reg = opc & 0x3; + u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1); g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); @@ -256,10 +257,10 @@ void ilrri(const UDSPInstruction& opc) // Move value from instruction memory pointed by addressing register // $arS to mid accumulator register $acD.m. Add corresponding indexing // register $ixS to addressing register $arS. -void ilrrn(const UDSPInstruction& opc) +void ilrrn(const UDSPInstruction opc) { - u16 reg = opc.hex & 0x3; - u16 dreg = DSP_REG_ACM0 + ((opc.hex >> 8) & 1); + u16 reg = opc & 0x3; + u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1); g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); diff --git a/Source/Core/DSPCore/Src/DspIntMisc.cpp b/Source/Core/DSPCore/Src/DspIntMisc.cpp index f400a6df08..81c0e9ef0f 100644 --- a/Source/Core/DSPCore/Src/DspIntMisc.cpp +++ b/Source/Core/DSPCore/Src/DspIntMisc.cpp @@ -29,10 +29,10 @@ namespace DSPInterpreter { // 0001 11dd ddds ssss // Move value from register $S to register $D. // FIXME: Perform additional operation depending on destination register. -void mrr(const UDSPInstruction& opc) +void mrr(const UDSPInstruction opc) { - u8 sreg = opc.hex & 0x1f; - u8 dreg = (opc.hex >> 5) & 0x1f; + u8 sreg = opc & 0x1f; + u8 dreg = (opc >> 5) & 0x1f; u16 val = dsp_op_read_reg(sreg); dsp_op_write_reg(dreg, val); @@ -49,9 +49,9 @@ void mrr(const UDSPInstruction& opc) // register, has a different behaviour in S40 mode if loaded to AC0.M: The // value gets sign extended to the whole accumulator! This does not happen in // S16 mode. -void lri(const UDSPInstruction& opc) +void lri(const UDSPInstruction opc) { - u8 reg = opc.hex & DSP_REG_MASK; + u8 reg = opc & DSP_REG_MASK; u16 imm = dsp_fetch_code(); dsp_op_write_reg(reg, imm); dsp_conditional_extend_accum(reg); @@ -61,10 +61,10 @@ void lri(const UDSPInstruction& opc) // 0000 1ddd iiii iiii // Load immediate value I (8-bit sign extended) to accumulator register. // FIXME: Perform additional operation depending on destination register. -void lris(const UDSPInstruction& opc) +void lris(const UDSPInstruction opc) { - u8 reg = ((opc.hex >> 8) & 0x7) + DSP_REG_AXL0; - u16 imm = (s8)opc.hex; + u8 reg = ((opc >> 8) & 0x7) + DSP_REG_AXL0; + u16 imm = (s8)opc; dsp_op_write_reg(reg, imm); dsp_conditional_extend_accum(reg); } @@ -76,7 +76,7 @@ void lris(const UDSPInstruction& opc) // No operation, but can be extended with extended opcode. // This opcode is supposed to do nothing - it's used if you want to use // an opcode extension but not do anything. At least according to duddie. -void nx(const UDSPInstruction& opc) +void nx(const UDSPInstruction opc) { zeroWriteBackLog(); } @@ -86,26 +86,26 @@ void nx(const UDSPInstruction& opc) // DAR $arD // 0000 0000 0000 01dd // Decrement address register $arD. -void dar(const UDSPInstruction& opc) +void dar(const UDSPInstruction opc) { - g_dsp.r[opc.hex & 0x3] = dsp_decrement_addr_reg(opc.hex & 0x3); + g_dsp.r[opc & 0x3] = dsp_decrement_addr_reg(opc & 0x3); } // IAR $arD // 0000 0000 0000 10dd // Increment address register $arD. -void iar(const UDSPInstruction& opc) +void iar(const UDSPInstruction opc) { - g_dsp.r[opc.hex & 0x3] = dsp_increment_addr_reg(opc.hex & 0x3); + g_dsp.r[opc & 0x3] = dsp_increment_addr_reg(opc & 0x3); } // SUBARN $arD // 0000 0000 0000 11dd // Subtract indexing register $ixD from an addressing register $arD. // used only in IPL-NTSC ucode -void subarn(const UDSPInstruction& opc) +void subarn(const UDSPInstruction opc) { - u8 dreg = opc.hex & 0x3; + u8 dreg = opc & 0x3; g_dsp.r[dreg] = dsp_decrease_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]); } @@ -113,10 +113,10 @@ void subarn(const UDSPInstruction& opc) // 0000 0000 0001 ssdd // Adds indexing register $ixS to an addressing register $arD. // It is critical for the Zelda ucode that this one wraps correctly. -void addarn(const UDSPInstruction& opc) +void addarn(const UDSPInstruction opc) { - u8 dreg = opc.hex & 0x3; - u8 sreg = (opc.hex >> 2) & 0x3; + u8 dreg = opc & 0x3; + u8 sreg = (opc >> 2) & 0x3; g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]); } @@ -126,9 +126,9 @@ void addarn(const UDSPInstruction& opc) // 0001 0011 aaaa aiii // bit of status register $sr. Bit number is calculated by adding 6 to // immediate value I. -void sbclr(const UDSPInstruction& opc) +void sbclr(const UDSPInstruction opc) { - u8 bit = (opc.hex & 0x7) + 6; + u8 bit = (opc & 0x7) + 6; g_dsp.r[DSP_REG_SR] &= ~(1 << bit); } @@ -136,18 +136,18 @@ void sbclr(const UDSPInstruction& opc) // 0001 0010 aaaa aiii // Set bit of status register $sr. Bit number is calculated by adding 6 to // immediate value I. -void sbset(const UDSPInstruction& opc) +void sbset(const UDSPInstruction opc) { - u8 bit = (opc.hex & 0x7) + 6; + u8 bit = (opc & 0x7) + 6; g_dsp.r[DSP_REG_SR] |= (1 << bit); } // This is a bunch of flag setters, flipping bits in SR. So far so good, // but it's harder to know exactly what effect they have. -void srbith(const UDSPInstruction& opc) +void srbith(const UDSPInstruction opc) { zeroWriteBackLog(); - switch ((opc.hex >> 8) & 0xf) + switch ((opc >> 8) & 0xf) { // M0/M2 change the multiplier mode (it can multiply by 2 for free). case 0xa: // M2 @@ -183,9 +183,9 @@ void srbith(const UDSPInstruction& opc) //---- -void unknown(const UDSPInstruction& opc) +void unknown(const UDSPInstruction opc) { - ERROR_LOG(DSPLLE, "LLE: Unrecognized opcode 0x%04x, pc 0x%04x", opc.hex, g_dsp.pc); + ERROR_LOG(DSPLLE, "LLE: Unrecognized opcode 0x%04x, pc 0x%04x", opc, g_dsp.pc); } } // namespace diff --git a/Source/Core/DSPCore/Src/DspIntMultiplier.cpp b/Source/Core/DSPCore/Src/DspIntMultiplier.cpp index d801dd6fc6..110673a976 100644 --- a/Source/Core/DSPCore/Src/DspIntMultiplier.cpp +++ b/Source/Core/DSPCore/Src/DspIntMultiplier.cpp @@ -103,7 +103,7 @@ s64 dsp_multiply_mulx(u8 axh0, u8 axh1, u16 val1, u16 val2) // CLRP // 1000 0100 xxxx xxxx // Clears product register $prod. -void clrp(const UDSPInstruction& opc) +void clrp(const UDSPInstruction opc) { // Magic numbers taken from duddie's doc // These are probably a bad idea to put here. @@ -123,7 +123,7 @@ void clrp(const UDSPInstruction& opc) // Test prod regs value. // // flags out: xx xx0x <- CF?? -void tstprod(const UDSPInstruction& opc) +void tstprod(const UDSPInstruction opc) { s64 prod = dsp_get_long_prod(); Update_SR_Register64(prod); @@ -137,9 +137,9 @@ void tstprod(const UDSPInstruction& opc) // Moves multiply product from $prod register to accumulator $acD register. // // flags out: xx xx00 -void movp(const UDSPInstruction& opc) +void movp(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = dsp_get_long_prod(); @@ -155,9 +155,9 @@ void movp(const UDSPInstruction& opc) // $acD register. // // flags out: xx xx0x <- CF?? -void movnp(const UDSPInstruction& opc) +void movnp(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; + u8 dreg = (opc >> 8) & 0x1; s64 acc = -dsp_get_long_prod(); @@ -173,9 +173,9 @@ void movnp(const UDSPInstruction& opc) // register and sets $acD.l to 0 // // flags out: xx xx0x <- CF?? -void movpz(const UDSPInstruction& opc) +void movpz(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x01; + u8 dreg = (opc >> 8) & 0x01; s64 acc = dsp_get_long_prod_round_prodl(); @@ -191,10 +191,10 @@ void movpz(const UDSPInstruction& opc) // in accumulator register. Low 16-bits of $acD ($acD.l) are set to 0. // // flags out: ?-xx xx?? -void addpaxz(const UDSPInstruction& opc) +void addpaxz(const UDSPInstruction opc) { - u8 dreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 dreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; s64 prod = dsp_get_long_prod_round_prodl(); s64 ax = dsp_get_long_acx(sreg); @@ -212,7 +212,7 @@ void addpaxz(const UDSPInstruction& opc) // MULAXH // 1000 0011 xxxx xxxx // Multiply $ax0.h by $ax0.h -void mulaxh(const UDSPInstruction& opc) +void mulaxh(const UDSPInstruction opc) { s64 prod = dsp_multiply(dsp_get_ax_h(0), dsp_get_ax_h(0)); @@ -227,9 +227,9 @@ void mulaxh(const UDSPInstruction& opc) // 1001 s000 xxxx xxxx // Multiply low part $axS.l of secondary accumulator $axS by high part // $axS.h of secondary accumulator $axS (treat them both as signed). -void mul(const UDSPInstruction& opc) +void mul(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 11) & 0x1; + u8 sreg = (opc >> 11) & 0x1; u16 axl = dsp_get_ax_l(sreg); u16 axh = dsp_get_ax_h(sreg); @@ -247,10 +247,10 @@ void mul(const UDSPInstruction& opc) // accumulator $axS (treat them both as signed). // // flags out: xx xx00 -void mulac(const UDSPInstruction& opc) +void mulac(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 11) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 11) & 0x1; s64 acc = dsp_get_long_acc(rreg) + dsp_get_long_prod(); u16 axl = dsp_get_ax_l(sreg); @@ -271,10 +271,10 @@ void mulac(const UDSPInstruction& opc) // accumulator $axS (treat them both as signed). // // flags out: xx xx00 -void mulmv(const UDSPInstruction& opc) +void mulmv(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 sreg = ((opc.hex >> 11) & 0x1); + u8 rreg = (opc >> 8) & 0x1; + u8 sreg = ((opc >> 11) & 0x1); s64 acc = dsp_get_long_prod(); u16 axl = dsp_get_ax_l(sreg); @@ -296,10 +296,10 @@ void mulmv(const UDSPInstruction& opc) // them both as signed). // // flags out: xx xx0x -void mulmvz(const UDSPInstruction& opc) +void mulmvz(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 11) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 11) & 0x1; s64 acc = dsp_get_long_prod_round_prodl(); u16 axl = dsp_get_ax_l(sreg); @@ -319,10 +319,10 @@ void mulmvz(const UDSPInstruction& opc) // 101s t000 xxxx xxxx // Multiply one part $ax0 by one part $ax1. // Part is selected by S and T bits. Zero selects low part, one selects high part. -void mulx(const UDSPInstruction& opc) +void mulx(const UDSPInstruction opc) { - u8 treg = ((opc.hex >> 11) & 0x1); - u8 sreg = ((opc.hex >> 12) & 0x1); + u8 treg = ((opc >> 11) & 0x1); + u8 sreg = ((opc >> 12) & 0x1); u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); @@ -340,11 +340,11 @@ void mulx(const UDSPInstruction& opc) // T bits. Zero selects low part, one selects high part. // // flags out: xx xx00 -void mulxac(const UDSPInstruction& opc) +void mulxac(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_acc(rreg) + dsp_get_long_prod(); u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); @@ -365,11 +365,11 @@ void mulxac(const UDSPInstruction& opc) // T bits. Zero selects low part, one selects high part. // // flags out: xx xx00 -void mulxmv(const UDSPInstruction& opc) +void mulxmv(const UDSPInstruction opc) { - u8 rreg = ((opc.hex >> 8) & 0x1); - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = ((opc >> 8) & 0x1); + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_prod(); u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); @@ -391,11 +391,11 @@ void mulxmv(const UDSPInstruction& opc) // one selects high part. // // flags out: xx xx00 -void mulxmvz(const UDSPInstruction& opc) +void mulxmvz(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_prod_round_prodl(); u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); @@ -415,10 +415,10 @@ void mulxmvz(const UDSPInstruction& opc) // 110s t000 xxxx xxxx // Multiply mid part of accumulator register $acS.m by high part $axS.h of // secondary accumulator $axS (treat them both as signed). -void mulc(const UDSPInstruction& opc) +void mulc(const UDSPInstruction opc) { - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; u16 accm = dsp_get_acc_m(sreg); u16 axh = dsp_get_ax_h(treg); @@ -436,11 +436,11 @@ void mulc(const UDSPInstruction& opc) // register before multiplication to accumulator $acR. // // flags out: xx xx00 -void mulcac(const UDSPInstruction& opc) +void mulcac(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_acc(rreg) + dsp_get_long_prod(); u16 accm = dsp_get_acc_m(sreg); @@ -462,11 +462,11 @@ void mulcac(const UDSPInstruction& opc) // possible mistake in duddie's doc axT.h rather than axS.h // // flags out: xx xx00 -void mulcmv(const UDSPInstruction& opc) +void mulcmv(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_prod(); u16 accm = dsp_get_acc_m(sreg); @@ -489,11 +489,11 @@ void mulcmv(const UDSPInstruction& opc) // accumulator $acR.l to zero. // // flags out: xx xx00 -void mulcmvz(const UDSPInstruction& opc) +void mulcmvz(const UDSPInstruction opc) { - u8 rreg = (opc.hex >> 8) & 0x1; - u8 treg = (opc.hex >> 11) & 0x1; - u8 sreg = (opc.hex >> 12) & 0x1; + u8 rreg = (opc >> 8) & 0x1; + u8 treg = (opc >> 11) & 0x1; + u8 sreg = (opc >> 12) & 0x1; s64 acc = dsp_get_long_prod_round_prodl(); u16 accm = dsp_get_acc_m(sreg); @@ -514,10 +514,10 @@ void mulcmvz(const UDSPInstruction& opc) // Multiply one part of secondary accumulator $ax0 (selected by S) by // one part of secondary accumulator $ax1 (selected by T) (treat them both as // signed) and add result to product register. -void maddx(const UDSPInstruction& opc) +void maddx(const UDSPInstruction opc) { - u8 treg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 treg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); @@ -533,10 +533,10 @@ void maddx(const UDSPInstruction& opc) // Multiply one part of secondary accumulator $ax0 (selected by S) by // one part of secondary accumulator $ax1 (selected by T) (treat them both as // signed) and subtract result from product register. -void msubx(const UDSPInstruction& opc) +void msubx(const UDSPInstruction opc) { - u8 treg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 treg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 val1 = (sreg == 0) ? dsp_get_ax_l(0) : dsp_get_ax_h(0); u16 val2 = (treg == 0) ? dsp_get_ax_l(1) : dsp_get_ax_h(1); @@ -552,10 +552,10 @@ void msubx(const UDSPInstruction& opc) // Multiply middle part of accumulator $acS.m by high part of secondary // accumulator $axT.h (treat them both as signed) and add result to product // register. -void maddc(const UDSPInstruction& opc) +void maddc(const UDSPInstruction opc) { - u8 treg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 treg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 accm = dsp_get_acc_m(sreg); u16 axh = dsp_get_ax_h(treg); @@ -571,10 +571,10 @@ void maddc(const UDSPInstruction& opc) // Multiply middle part of accumulator $acS.m by high part of secondary // accumulator $axT.h (treat them both as signed) and subtract result from // product register. -void msubc(const UDSPInstruction& opc) +void msubc(const UDSPInstruction opc) { - u8 treg = (opc.hex >> 8) & 0x1; - u8 sreg = (opc.hex >> 9) & 0x1; + u8 treg = (opc >> 8) & 0x1; + u8 sreg = (opc >> 9) & 0x1; u16 accm = dsp_get_acc_m(sreg); u16 axh = dsp_get_ax_h(treg); @@ -590,9 +590,9 @@ void msubc(const UDSPInstruction& opc) // Multiply low part $axS.l of secondary accumulator $axS by high part // $axS.h of secondary accumulator $axS (treat them both as signed) and add // result to product register. -void madd(const UDSPInstruction& opc) +void madd(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 8) & 0x1; + u8 sreg = (opc >> 8) & 0x1; u16 axl = dsp_get_ax_l(sreg); u16 axh = dsp_get_ax_h(sreg); @@ -608,9 +608,9 @@ void madd(const UDSPInstruction& opc) // Multiply low part $axS.l of secondary accumulator $axS by high part // $axS.h of secondary accumulator $axS (treat them both as signed) and // subtract result from product register. -void msub(const UDSPInstruction& opc) +void msub(const UDSPInstruction opc) { - u8 sreg = (opc.hex >> 8) & 0x1; + u8 sreg = (opc >> 8) & 0x1; u16 axl = dsp_get_ax_l(sreg); u16 axh = dsp_get_ax_h(sreg); diff --git a/Source/Core/DSPCore/Src/disassemble.cpp b/Source/Core/DSPCore/Src/disassemble.cpp index aef78c866a..b64091186c 100644 --- a/Source/Core/DSPCore/Src/disassemble.cpp +++ b/Source/Core/DSPCore/Src/disassemble.cpp @@ -39,7 +39,7 @@ #include // For MAX_PATH #endif -extern void nop(const UDSPInstruction& opc); +extern void nop(const UDSPInstruction opc); DSPDisassembler::DSPDisassembler(const AssemblerSettings &settings) : settings_(settings)