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[AArch64] Minor shifted register adjustment. 

If we have a shift amount that is the full length of the source register then we have an invalid instruction.
This can happen when dealing with a couple of PowerPC instructions.
This same adjustment is already in the ARMv7 emitter.
This commit is contained in:
Ryan Houdek 2015-01-07 13:03:51 -06:00
parent 0a23ca9461
commit 2b4f1aed40
1 changed files with 8 additions and 0 deletions
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8
Source/Core/Common/Arm64Emitter.h
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@ -238,9 +238,17 @@ public:
m_shifttype = shift_type; m_shifttype = shift_type;
m_type = TYPE_SHIFTEDREG; m_type = TYPE_SHIFTEDREG;
if (Is64Bit(Rd)) if (Is64Bit(Rd))
{
m_width = WIDTH_64BIT; m_width = WIDTH_64BIT;
if (shift == 64)
m_shift = 0;
}
else else
{
m_width = WIDTH_32BIT; m_width = WIDTH_32BIT;
if (shift == 32)
m_shift = 0;
}
} }
TypeSpecifier GetType() const TypeSpecifier GetType() const
{ {