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Merge pull request #9448 from JosJuice/blr-x30 

JitArm64: Avoid using X30 with BLR
This commit is contained in:
Markus Wick 2021-01-27 20:07:24 +01:00 committed by GitHub
parent 8c127a612f 67491979ab
commit 2ada5b422d
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 47 additions and 47 deletions
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8
Source/Core/Common/Arm64Emitter.h
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@ -912,14 +912,14 @@ public:
} }
// This function expects you to have set up the state. // This function expects you to have set up the state.
// Overwrites X0 and X30 // Overwrites X0 and X8
template <typename T, typename... Args> template <typename T, typename... Args>
ARM64Reg ABI_SetupLambda(const std::function<T(Args...)>* f) ARM64Reg ABI_SetupLambda(const std::function<T(Args...)>* f)
{ {
auto trampoline = &ARM64XEmitter::CallLambdaTrampoline<T, Args...>; auto trampoline = &ARM64XEmitter::CallLambdaTrampoline<T, Args...>;
MOVI2R(X30, (uintptr_t)trampoline); MOVP2R(X8, trampoline);
MOVI2R(X0, (uintptr_t) const_cast<void*>((const void*)f)); MOVP2R(X0, const_cast<void*>((const void*)f));
return X30; return X8;
} }
// Plain function call // Plain function call

22
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
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@ -157,9 +157,9 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
} }
Interpreter::Instruction instr = PPCTables::GetInterpreterOp(inst); Interpreter::Instruction instr = PPCTables::GetInterpreterOp(inst);
MOVP2R(X8, instr);
MOVI2R(W0, inst.hex); MOVI2R(W0, inst.hex);
MOVP2R(X30, instr); BLR(X8);
BLR(X30);
if (js.op->opinfo->flags & FL_ENDBLOCK) if (js.op->opinfo->flags & FL_ENDBLOCK)
{ {
@ -213,10 +213,10 @@ void JitArm64::HLEFunction(u32 hook_index)
gpr.Flush(FlushMode::All); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::All); fpr.Flush(FlushMode::All);
MOVP2R(X8, &HLE::Execute);
MOVI2R(W0, js.compilerPC); MOVI2R(W0, js.compilerPC);
MOVI2R(W1, hook_index); MOVI2R(W1, hook_index);
MOVP2R(X30, &HLE::Execute); BLR(X8);
BLR(X30);
} }
void JitArm64::DoNothing(UGeckoInstruction inst) void JitArm64::DoNothing(UGeckoInstruction inst)
@ -246,11 +246,11 @@ void JitArm64::Cleanup()
// SPEED HACK: MMCR0/MMCR1 should be checked at run-time, not at compile time. // SPEED HACK: MMCR0/MMCR1 should be checked at run-time, not at compile time.
if (MMCR0.Hex || MMCR1.Hex) if (MMCR0.Hex || MMCR1.Hex)
{ {
MOVP2R(X30, &PowerPC::UpdatePerformanceMonitor); MOVP2R(X8, &PowerPC::UpdatePerformanceMonitor);
MOVI2R(X0, js.downcountAmount); MOVI2R(X0, js.downcountAmount);
MOVI2R(X1, js.numLoadStoreInst); MOVI2R(X1, js.numLoadStoreInst);
MOVI2R(X2, js.numFloatingPointInst); MOVI2R(X2, js.numFloatingPointInst);
BLR(X30); BLR(X8);
} }
} }
@ -453,10 +453,10 @@ void JitArm64::WriteExceptionExit(u32 destination, bool only_external)
STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc)); STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc));
STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(npc)); STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(npc));
if (only_external) if (only_external)
MOVP2R(X30, &PowerPC::CheckExternalExceptions); MOVP2R(X8, &PowerPC::CheckExternalExceptions);
else else
MOVP2R(X30, &PowerPC::CheckExceptions); MOVP2R(X8, &PowerPC::CheckExceptions);
BLR(X30); BLR(X8);
LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(npc)); LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(npc));
SetJumpTarget(no_exceptions); SetJumpTarget(no_exceptions);
@ -723,8 +723,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
SetJumpTarget(Exception); SetJumpTarget(Exception);
ABI_PushRegisters(regs_in_use); ABI_PushRegisters(regs_in_use);
m_float_emit.ABI_PushRegisters(fprs_in_use, X30); m_float_emit.ABI_PushRegisters(fprs_in_use, X30);
MOVP2R(X30, &GPFifo::FastCheckGatherPipe); MOVP2R(X8, &GPFifo::FastCheckGatherPipe);
BLR(X30); BLR(X8);
m_float_emit.ABI_PopRegisters(fprs_in_use, X30); m_float_emit.ABI_PopRegisters(fprs_in_use, X30);
ABI_PopRegisters(regs_in_use); ABI_PopRegisters(regs_in_use);

48
Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp
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@ -187,49 +187,49 @@ void JitArm64::EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode, AR
{ {
m_float_emit.FCVT(32, 64, D0, RS); m_float_emit.FCVT(32, 64, D0, RS);
m_float_emit.UMOV(32, W0, Q0, 0); m_float_emit.UMOV(32, W0, Q0, 0);
MOVP2R(X30, &PowerPC::Write_U32); MOVP2R(X8, &PowerPC::Write_U32);
BLR(X30); BLR(X8);
} }
else if (flags & BackPatchInfo::FLAG_SIZE_F32I) else if (flags & BackPatchInfo::FLAG_SIZE_F32I)
{ {
m_float_emit.UMOV(32, W0, RS, 0); m_float_emit.UMOV(32, W0, RS, 0);
MOVP2R(X30, &PowerPC::Write_U32); MOVP2R(X8, &PowerPC::Write_U32);
BLR(X30); BLR(X8);
} }
else if (flags & BackPatchInfo::FLAG_SIZE_F32X2) else if (flags & BackPatchInfo::FLAG_SIZE_F32X2)
{ {
m_float_emit.FCVTN(32, D0, RS); m_float_emit.FCVTN(32, D0, RS);
m_float_emit.UMOV(64, X0, D0, 0); m_float_emit.UMOV(64, X0, D0, 0);
ROR(X0, X0, 32); ROR(X0, X0, 32);
MOVP2R(X30, &PowerPC::Write_U64); MOVP2R(X8, &PowerPC::Write_U64);
BLR(X30); BLR(X8);
} }
else if (flags & BackPatchInfo::FLAG_SIZE_F32X2I) else if (flags & BackPatchInfo::FLAG_SIZE_F32X2I)
{ {
m_float_emit.UMOV(64, X0, RS, 0); m_float_emit.UMOV(64, X0, RS, 0);
ROR(X0, X0, 32); ROR(X0, X0, 32);
MOVP2R(X30, &PowerPC::Write_U64); MOVP2R(X8, &PowerPC::Write_U64);
BLR(X30); BLR(X8);
} }
else else
{ {
MOVP2R(X30, &PowerPC::Write_U64); MOVP2R(X8, &PowerPC::Write_U64);
m_float_emit.UMOV(64, X0, RS, 0); m_float_emit.UMOV(64, X0, RS, 0);
BLR(X30); BLR(X8);
} }
} }
else if (flags & BackPatchInfo::FLAG_LOAD && flags & BackPatchInfo::FLAG_MASK_FLOAT) else if (flags & BackPatchInfo::FLAG_LOAD && flags & BackPatchInfo::FLAG_MASK_FLOAT)
{ {
if (flags & BackPatchInfo::FLAG_SIZE_F32) if (flags & BackPatchInfo::FLAG_SIZE_F32)
{ {
MOVP2R(X30, &PowerPC::Read_U32); MOVP2R(X8, &PowerPC::Read_U32);
BLR(X30); BLR(X8);
m_float_emit.INS(32, RS, 0, X0); m_float_emit.INS(32, RS, 0, X0);
} }
else else
{ {
MOVP2R(X30, &PowerPC::Read_F64); MOVP2R(X8, &PowerPC::Read_F64);
BLR(X30); BLR(X8);
m_float_emit.INS(64, RS, 0, X0); m_float_emit.INS(64, RS, 0, X0);
} }
} }
@ -238,29 +238,29 @@ void JitArm64::EmitBackpatchRoutine(u32 flags, bool fastmem, bool do_farcode, AR
MOV(W0, RS); MOV(W0, RS);
if (flags & BackPatchInfo::FLAG_SIZE_32) if (flags & BackPatchInfo::FLAG_SIZE_32)
MOVP2R(X30, &PowerPC::Write_U32); MOVP2R(X8, &PowerPC::Write_U32);
else if (flags & BackPatchInfo::FLAG_SIZE_16) else if (flags & BackPatchInfo::FLAG_SIZE_16)
MOVP2R(X30, &PowerPC::Write_U16); MOVP2R(X8, &PowerPC::Write_U16);
else else
MOVP2R(X30, &PowerPC::Write_U8); MOVP2R(X8, &PowerPC::Write_U8);
BLR(X30); BLR(X8);
} }
else if (flags & BackPatchInfo::FLAG_ZERO_256) else if (flags & BackPatchInfo::FLAG_ZERO_256)
{ {
MOVP2R(X30, &PowerPC::ClearCacheLine); MOVP2R(X8, &PowerPC::ClearCacheLine);
BLR(X30); BLR(X8);
} }
else else
{ {
if (flags & BackPatchInfo::FLAG_SIZE_32) if (flags & BackPatchInfo::FLAG_SIZE_32)
MOVP2R(X30, &PowerPC::Read_U32); MOVP2R(X8, &PowerPC::Read_U32);
else if (flags & BackPatchInfo::FLAG_SIZE_16) else if (flags & BackPatchInfo::FLAG_SIZE_16)
MOVP2R(X30, &PowerPC::Read_U16); MOVP2R(X8, &PowerPC::Read_U16);
else if (flags & BackPatchInfo::FLAG_SIZE_8) else if (flags & BackPatchInfo::FLAG_SIZE_8)
MOVP2R(X30, &PowerPC::Read_U8); MOVP2R(X8, &PowerPC::Read_U8);
BLR(X30); BLR(X8);
if (!(flags & BackPatchInfo::FLAG_REVERSE)) if (!(flags & BackPatchInfo::FLAG_REVERSE))
{ {

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View File

@ -82,8 +82,8 @@ void JitArm64::psq_l(UGeckoInstruction inst)
UBFM(scale_reg, scale_reg, 24, 29); // Scale UBFM(scale_reg, scale_reg, 24, 29); // Scale
MOVP2R(X30, inst.W ? single_load_quantized : paired_load_quantized); MOVP2R(X30, inst.W ? single_load_quantized : paired_load_quantized);
LDR(X30, X30, ArithOption(EncodeRegTo64(type_reg), true)); LDR(EncodeRegTo64(type_reg), X30, ArithOption(EncodeRegTo64(type_reg), true));
BLR(X30); BLR(EncodeRegTo64(type_reg));
VS = fpr.RW(inst.RS, RegType::Single); VS = fpr.RW(inst.RS, RegType::Single);
m_float_emit.ORR(EncodeRegToDouble(VS), D0, D0); m_float_emit.ORR(EncodeRegToDouble(VS), D0, D0);

12
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
View File

@ -125,9 +125,9 @@ void JitArm64::GenerateAsm()
// Call C version of Dispatch(). // Call C version of Dispatch().
STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc)); STR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc));
MOVP2R(X8, reinterpret_cast<void*>(&JitBase::Dispatch));
MOVP2R(X0, this); MOVP2R(X0, this);
MOVP2R(X30, reinterpret_cast<void*>(&JitBase::Dispatch)); BLR(X8);
BLR(X30);
FixupBranch no_block_available = CBZ(X0); FixupBranch no_block_available = CBZ(X0);
@ -145,8 +145,8 @@ void JitArm64::GenerateAsm()
ResetStack(); ResetStack();
MOVP2R(X0, this); MOVP2R(X0, this);
MOV(W1, DISPATCHER_PC); MOV(W1, DISPATCHER_PC);
MOVP2R(X30, reinterpret_cast<void*>(&JitTrampoline)); MOVP2R(X8, reinterpret_cast<void*>(&JitTrampoline));
BLR(X30); BLR(X8);
LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc)); LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc));
B(dispatcher_no_check); B(dispatcher_no_check);
@ -165,8 +165,8 @@ void JitArm64::GenerateAsm()
FixupBranch Exit = B(CC_NEQ); FixupBranch Exit = B(CC_NEQ);
SetJumpTarget(to_start_of_timing_slice); SetJumpTarget(to_start_of_timing_slice);
MOVP2R(X30, &CoreTiming::Advance); MOVP2R(X8, &CoreTiming::Advance);
BLR(X30); BLR(X8);
// Load the PC back into DISPATCHER_PC (the exception handler might have changed it) // Load the PC back into DISPATCHER_PC (the exception handler might have changed it)
LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc)); LDR(IndexType::Unsigned, DISPATCHER_PC, PPC_REG, PPCSTATE_OFF(pc));