Merge pull request #7287 from degasus/idle_skipping
Jit64 / JitArm64: Optimized idle skipping detection.
This commit is contained in:
commit
2abe333ce9
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@ -181,6 +181,15 @@ static bool CheckBreakpoint(u32 data)
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return false;
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}
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static bool CheckIdle(u32 idle_pc)
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{
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if (PowerPC::ppcState.npc == idle_pc)
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{
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CoreTiming::Idle();
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}
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return false;
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}
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bool CachedInterpreter::HandleFunctionHooking(u32 address)
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{
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return HLE::ReplaceFunctionIfPossible(address, [&](u32 function, HLE::HookType type) {
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@ -242,6 +251,7 @@ void CachedInterpreter::Jit(u32 address)
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const bool check_fpu = (op.opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound;
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const bool endblock = (op.opinfo->flags & FL_ENDBLOCK) != 0;
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const bool memcheck = (op.opinfo->flags & FL_LOADSTORE) && jo.memcheck;
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const bool idle_loop = op.branchIsIdleLoop;
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if (breakpoint)
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{
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@ -261,6 +271,8 @@ void CachedInterpreter::Jit(u32 address)
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m_code.emplace_back(PPCTables::GetInterpreterOp(op.inst), op.inst);
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if (memcheck)
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m_code.emplace_back(CheckDSI, js.downcountAmount);
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if (idle_loop)
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m_code.emplace_back(CheckIdle, js.blockStart);
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if (endblock)
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m_code.emplace_back(EndBlock, js.downcountAmount);
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}
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@ -5,7 +5,6 @@
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#include "Common/Assert.h"
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#include "Common/CommonTypes.h"
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#include "Core/ConfigManager.h"
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#include "Core/CoreTiming.h"
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#include "Core/HLE/HLE.h"
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#include "Core/PowerPC/Interpreter/ExceptionUtils.h"
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#include "Core/PowerPC/Interpreter/Interpreter.h"
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@ -23,11 +22,6 @@ void Interpreter::bx(UGeckoInstruction inst)
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NPC = PC + SignExt26(inst.LI << 2);
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m_end_block = true;
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if (NPC == PC)
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{
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CoreTiming::Idle();
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}
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}
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// bcx - ugly, straight from PPC manual equations :)
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@ -56,24 +50,6 @@ void Interpreter::bcx(UGeckoInstruction inst)
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}
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m_end_block = true;
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// this code trys to detect the most common idle loop:
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// lwz r0, XXXX(r13)
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// cmpXwi r0,0
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// beq -8
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if (NPC == PC - 8 && inst.hex == 0x4182fff8 /* beq */)
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{
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if (PowerPC::HostRead_U32(PC - 8) >> 16 == 0x800D /* lwz */)
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{
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u32 last_inst = PowerPC::HostRead_U32(PC - 4);
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if (last_inst == 0x28000000 /* cmplwi */ ||
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(last_inst == 0x2C000000 /* cmpwi */ && SConfig::GetInstance().bWii))
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{
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CoreTiming::Idle();
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}
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}
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}
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}
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void Interpreter::bcctrx(UGeckoInstruction inst)
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@ -29,8 +29,8 @@ static std::array<GekkoOPTemplate, 54> primarytable =
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{59, Interpreter::RunTable59, {"RunTable59", OpType::Subtable, 0, 0, 0, 0, 0}},
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{63, Interpreter::RunTable63, {"RunTable63", OpType::Subtable, 0, 0, 0, 0, 0}},
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{16, Interpreter::bcx, {"bcx", OpType::System, FL_ENDBLOCK, 1, 0, 0, 0}},
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{18, Interpreter::bx, {"bx", OpType::System, FL_ENDBLOCK, 1, 0, 0, 0}},
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{16, Interpreter::bcx, {"bcx", OpType::Branch, FL_ENDBLOCK, 1, 0, 0, 0}},
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{18, Interpreter::bx, {"bx", OpType::Branch, FL_ENDBLOCK, 1, 0, 0, 0}},
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{3, Interpreter::twi, {"twi", OpType::System, FL_ENDBLOCK, 1, 0, 0, 0}},
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{17, Interpreter::sc, {"sc", OpType::System, FL_ENDBLOCK, 2, 0, 0, 0}},
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@ -646,6 +646,15 @@ void Jit64::WriteRfiExitDestInRSCRATCH()
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JMP(asm_routines.dispatcher, true);
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}
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void Jit64::WriteIdleExit(u32 destination)
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{
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ABI_PushRegistersAndAdjustStack({}, 0);
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ABI_CallFunction(CoreTiming::Idle);
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ABI_PopRegistersAndAdjustStack({}, 0);
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MOV(32, PPCSTATE(pc), Imm32(destination));
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WriteExceptionExit();
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}
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void Jit64::WriteExceptionExit()
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{
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Cleanup();
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@ -84,6 +84,7 @@ public:
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void WriteExceptionExit();
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void WriteExternalExceptionExit();
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void WriteRfiExitDestInRSCRATCH();
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void WriteIdleExit(u32 destination);
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bool Cleanup();
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void GenerateConstantOverflow(bool overflow);
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@ -87,25 +87,18 @@ void Jit64::bx(UGeckoInstruction inst)
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gpr.Flush();
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fpr.Flush();
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u32 destination;
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if (inst.AA)
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destination = SignExt26(inst.LI << 2);
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else
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destination = js.compilerPC + SignExt26(inst.LI << 2);
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#ifdef ACID_TEST
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if (inst.LK)
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AND(32, PPCSTATE(cr), Imm32(~(0xFF000000)));
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#endif
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if (destination == js.compilerPC)
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if (js.op->branchIsIdleLoop)
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{
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ABI_PushRegistersAndAdjustStack({}, 0);
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ABI_CallFunction(CoreTiming::Idle);
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ABI_PopRegistersAndAdjustStack({}, 0);
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MOV(32, PPCSTATE(pc), Imm32(destination));
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WriteExceptionExit();
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return;
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WriteIdleExit(js.op->branchTo);
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}
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else
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{
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WriteExit(js.op->branchTo, inst.LK, js.compilerPC + 4);
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}
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WriteExit(destination, inst.LK, js.compilerPC + 4);
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}
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// TODO - optimize to hell and beyond
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@ -154,18 +147,20 @@ void Jit64::bcx(UGeckoInstruction inst)
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return;
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}
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u32 destination;
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if (inst.AA)
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destination = SignExt16(inst.BD << 2);
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else
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destination = js.compilerPC + SignExt16(inst.BD << 2);
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{
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RCForkGuard gpr_guard = gpr.Fork();
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RCForkGuard fpr_guard = fpr.Fork();
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gpr.Flush();
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fpr.Flush();
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WriteExit(destination, inst.LK, js.compilerPC + 4);
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if (js.op->branchIsIdleLoop)
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{
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WriteIdleExit(js.op->branchTo);
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}
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else
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{
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WriteExit(js.op->branchTo, inst.LK, js.compilerPC + 4);
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}
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}
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if ((inst.BO & BO_DONT_CHECK_CONDITION) == 0)
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@ -282,7 +277,15 @@ void Jit64::bclrx(UGeckoInstruction inst)
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RCForkGuard fpr_guard = fpr.Fork();
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gpr.Flush();
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fpr.Flush();
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WriteBLRExit();
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if (js.op->branchIsIdleLoop)
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{
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WriteIdleExit(js.op->branchTo);
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}
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else
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{
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WriteBLRExit();
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}
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}
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if ((inst.BO & BO_DONT_CHECK_CONDITION) == 0)
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@ -12,6 +12,7 @@
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#include "Common/CommonTypes.h"
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#include "Common/MathUtil.h"
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#include "Common/x64Emitter.h"
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#include "Core/CoreTiming.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64/RegCache/JitRegCache.h"
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#include "Core/PowerPC/Jit64Common/Jit64PowerPCState.h"
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@ -361,7 +362,15 @@ void Jit64::DoMergedBranch()
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// Code that handles successful PPC branching.
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const UGeckoInstruction& next = js.op[1].inst;
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const u32 nextPC = js.op[1].address;
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if (next.OPCD == 16) // bcx
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if (js.op[1].branchIsIdleLoop)
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{
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if (next.LK)
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MOV(32, PPCSTATE(spr[SPR_LR]), Imm32(nextPC + 4));
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WriteIdleExit(js.op[1].branchTo);
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}
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else if (next.OPCD == 16) // bcx
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{
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if (next.LK)
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MOV(32, PPCSTATE(spr[SPR_LR]), Imm32(nextPC + 4));
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@ -119,41 +119,6 @@ void Jit64::lXXx(UGeckoInstruction inst)
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signExtend = true;
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}
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if (!CPU::IsStepping() && inst.OPCD == 32 && CanMergeNextInstructions(2) &&
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(inst.hex & 0xFFFF0000) == 0x800D0000 &&
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(js.op[1].inst.hex == 0x28000000 ||
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(SConfig::GetInstance().bWii && js.op[1].inst.hex == 0x2C000000)) &&
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js.op[2].inst.hex == 0x4182fff8)
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{
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s32 offset = (s32)(s16)inst.SIMM_16;
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RCX64Reg Ra = gpr.Bind(a, RCMode::Read);
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RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
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RegCache::Realize(Ra, Rd);
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SafeLoadToReg(Rd, Ra, accessSize, offset, CallerSavedRegistersInUse(), signExtend);
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// if it's still 0, we can wait until the next event
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TEST(32, Rd, Rd);
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FixupBranch noIdle = J_CC(CC_NZ);
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BitSet32 registersInUse = CallerSavedRegistersInUse();
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ABI_PushRegistersAndAdjustStack(registersInUse, 0);
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ABI_CallFunction(CoreTiming::Idle);
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ABI_PopRegistersAndAdjustStack(registersInUse, 0);
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// ! we must continue executing of the loop after exception handling, maybe there is still 0 in
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// r0
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// MOV(32, PPCSTATE(pc), Imm32(js.compilerPC));
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WriteExceptionExit();
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SetJumpTarget(noIdle);
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// js.compilerPC += 8;
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return;
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}
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// Determine whether this instruction updates inst.RA
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bool update;
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if (inst.OPCD == 31)
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@ -76,12 +76,6 @@ void JitArm64::bx(UGeckoInstruction inst)
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INSTRUCTION_START
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JITDISABLE(bJITBranchOff);
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u32 destination;
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if (inst.AA)
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destination = SignExt26(inst.LI << 2);
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else
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destination = js.compilerPC + SignExt26(inst.LI << 2);
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if (inst.LK)
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{
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ARM64Reg WA = gpr.GetReg();
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@ -105,7 +99,7 @@ void JitArm64::bx(UGeckoInstruction inst)
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gpr.Flush(FlushMode::FLUSH_ALL);
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fpr.Flush(FlushMode::FLUSH_ALL);
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if (destination == js.compilerPC)
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if (js.op->branchIsIdleLoop)
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{
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// make idle loops go faster
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ARM64Reg WA = gpr.GetReg();
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@ -115,11 +109,11 @@ void JitArm64::bx(UGeckoInstruction inst)
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BLR(XA);
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gpr.Unlock(WA);
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WriteExceptionExit(js.compilerPC);
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WriteExceptionExit(js.op->branchTo);
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return;
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}
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WriteExit(destination, inst.LK, js.compilerPC + 4);
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WriteExit(js.op->branchTo, inst.LK, js.compilerPC + 4);
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}
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void JitArm64::bcx(UGeckoInstruction inst)
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@ -160,16 +154,25 @@ void JitArm64::bcx(UGeckoInstruction inst)
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}
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gpr.Unlock(WA);
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u32 destination;
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if (inst.AA)
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destination = SignExt16(inst.BD << 2);
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else
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destination = js.compilerPC + SignExt16(inst.BD << 2);
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gpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE);
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fpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE);
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WriteExit(destination, inst.LK, js.compilerPC + 4);
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if (js.op->branchIsIdleLoop)
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{
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// make idle loops go faster
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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MOVP2R(XA, &CoreTiming::Idle);
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BLR(XA);
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gpr.Unlock(WA);
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WriteExceptionExit(js.op->branchTo);
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}
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else
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{
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WriteExit(js.op->branchTo, inst.LK, js.compilerPC + 4);
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}
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SwitchToNearCode();
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@ -275,7 +278,20 @@ void JitArm64::bclrx(UGeckoInstruction inst)
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gpr.Flush(conditional ? FlushMode::FLUSH_MAINTAIN_STATE : FlushMode::FLUSH_ALL);
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fpr.Flush(conditional ? FlushMode::FLUSH_MAINTAIN_STATE : FlushMode::FLUSH_ALL);
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WriteBLRExit(WA);
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if (js.op->branchIsIdleLoop)
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{
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// make idle loops go faster
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ARM64Reg XA = EncodeRegTo64(WA);
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MOVP2R(XA, &CoreTiming::Idle);
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BLR(XA);
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WriteExceptionExit(js.op->branchTo);
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}
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else
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{
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WriteBLRExit(WA);
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}
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gpr.Unlock(WA);
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@ -346,37 +346,6 @@ void JitArm64::lXX(UGeckoInstruction inst)
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}
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SafeLoadToReg(d, update ? a : (a ? a : -1), offsetReg, flags, offset, update);
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// LWZ idle skipping
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if (inst.OPCD == 32 && CanMergeNextInstructions(2) &&
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(inst.hex & 0xFFFF0000) == 0x800D0000 && // lwz r0, XXXX(r13)
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(js.op[1].inst.hex == 0x28000000 ||
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(SConfig::GetInstance().bWii && js.op[1].inst.hex == 0x2C000000)) && // cmpXwi r0,0
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js.op[2].inst.hex == 0x4182fff8) // beq -8
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{
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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// if it's still 0, we can wait until the next event
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FixupBranch noIdle = CBNZ(gpr.R(d));
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FixupBranch far = B();
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SwitchToFarCode();
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SetJumpTarget(far);
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gpr.Flush(FLUSH_MAINTAIN_STATE);
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fpr.Flush(FLUSH_MAINTAIN_STATE);
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MOVP2R(XA, &CoreTiming::Idle);
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BLR(XA);
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gpr.Unlock(WA);
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WriteExceptionExit(js.compilerPC);
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SwitchToNearCode();
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SetJumpTarget(noIdle);
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}
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}
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void JitArm64::stX(UGeckoInstruction inst)
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@ -640,6 +640,90 @@ void PPCAnalyzer::SetInstructionStats(CodeBlock* block, CodeOp* code, const Gekk
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code->outputCR0 = true;
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code->outputCR1 = true;
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}
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code->branchUsesCtr = false;
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code->branchTo = UINT32_MAX;
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// For branch with immediate addresses (bx/bcx), compute the destination.
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if (code->inst.OPCD == 18) // bx
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{
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if (code->inst.AA) // absolute
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code->branchTo = SignExt26(code->inst.LI << 2);
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else
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code->branchTo = code->address + SignExt26(code->inst.LI << 2);
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}
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else if (code->inst.OPCD == 16) // bcx
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{
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if (code->inst.AA) // absolute
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code->branchTo = SignExt16(code->inst.BD << 2);
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else
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code->branchTo = code->address + SignExt16(code->inst.BD << 2);
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if (!(code->inst.BO & BO_DONT_DECREMENT_FLAG))
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code->branchUsesCtr = true;
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}
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else if (code->inst.OPCD == 19 && code->inst.SUBOP10 == 16) // bclrx
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{
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if (!(code->inst.BO & BO_DONT_DECREMENT_FLAG))
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code->branchUsesCtr = true;
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}
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else if (code->inst.OPCD == 19 && code->inst.SUBOP10 == 528) // bcctrx
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{
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if (!(code->inst.BO & BO_DONT_DECREMENT_FLAG))
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code->branchUsesCtr = true;
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}
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}
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bool PPCAnalyzer::IsBusyWaitLoop(CodeBlock* block, CodeOp* code, size_t instructions)
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{
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// Very basic algorithm to detect busy wait loops:
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// * It loops to itself and does not contain any other branches.
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// * It does not write to memory.
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// * It only reads from registers it wrote to earlier in the loop, or it
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// does not write to these registers.
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//
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// Would benefit a lot from basic inlining support - a lot of the most
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// used busy loops are DSP register interactions, which are bl/cmp/bne
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// (with the bl target a pure function that follows the above rules). We
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// don't detect these at the moment.
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std::bitset<32> write_disallowed_regs;
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std::bitset<32> written_regs;
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for (size_t i = 0; i <= instructions; ++i)
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{
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if (code[i].opinfo->type == OpType::Branch)
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{
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if (code[i].branchUsesCtr)
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return false;
|
||||
if (code[i].branchTo == block->m_address && i == instructions)
|
||||
return true;
|
||||
}
|
||||
else if (code[i].opinfo->type != OpType::Integer && code[i].opinfo->type != OpType::Load)
|
||||
{
|
||||
// In the future, some subsets of other instruction types might get
|
||||
// supported. Right now, only try loops that have this very
|
||||
// restricted instruction set.
|
||||
return false;
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int reg : code[i].regsIn)
|
||||
{
|
||||
if (reg == -1)
|
||||
continue;
|
||||
if (written_regs[reg])
|
||||
continue;
|
||||
write_disallowed_regs[reg] = true;
|
||||
}
|
||||
for (int reg : code[i].regsOut)
|
||||
{
|
||||
if (reg == -1)
|
||||
continue;
|
||||
if (write_disallowed_regs[reg])
|
||||
return false;
|
||||
written_regs[reg] = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std::size_t block_size)
|
||||
|
@ -692,8 +776,6 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std:
|
|||
code[i].opinfo = opinfo;
|
||||
code[i].address = address;
|
||||
code[i].inst = inst;
|
||||
code[i].branchTo = UINT32_MAX;
|
||||
code[i].branchToIndex = UINT32_MAX;
|
||||
code[i].skip = false;
|
||||
block->m_stats->numCycles += opinfo->numCycles;
|
||||
block->m_physical_addresses.insert(result.physical_address);
|
||||
|
@ -701,7 +783,6 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std:
|
|||
SetInstructionStats(block, &code[i], opinfo, static_cast<u32>(i));
|
||||
|
||||
bool follow = false;
|
||||
u32 destination = 0;
|
||||
|
||||
bool conditional_continue = false;
|
||||
|
||||
|
@ -709,13 +790,12 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std:
|
|||
// If it is small, the performance will be down.
|
||||
// If it is big, the size of generated code will be big and
|
||||
// cache clearning will happen many times.
|
||||
if (enable_follow && HasOption(OPTION_BRANCH_FOLLOW) && numFollows < BRANCH_FOLLOWING_THRESHOLD)
|
||||
if (enable_follow && HasOption(OPTION_BRANCH_FOLLOW))
|
||||
{
|
||||
if (inst.OPCD == 18 && block_size > 1)
|
||||
{
|
||||
// Always follow BX instructions.
|
||||
follow = true;
|
||||
destination = SignExt26(inst.LI << 2) + (inst.AA ? 0 : address);
|
||||
if (inst.LK)
|
||||
{
|
||||
found_call = true;
|
||||
|
@ -727,29 +807,31 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std:
|
|||
{
|
||||
// Always follow unconditional BCX instructions, but they are very rare.
|
||||
follow = true;
|
||||
destination = SignExt16(inst.BD << 2) + (inst.AA ? 0 : address);
|
||||
if (inst.LK)
|
||||
{
|
||||
found_call = true;
|
||||
caller = i;
|
||||
}
|
||||
}
|
||||
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 && !inst.LK && found_call &&
|
||||
(inst.BO & BO_DONT_DECREMENT_FLAG) && (inst.BO & BO_DONT_CHECK_CONDITION))
|
||||
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 && !inst.LK && found_call)
|
||||
{
|
||||
// bclrx with unconditional branch = return
|
||||
// Follow it if we can propagate the LR value of the last CALL instruction.
|
||||
// Through it would be easy to track the upper level of call/return,
|
||||
// we can't guarantee the LR value. The PPC ABI forces all functions to push
|
||||
// the LR value on the stack as there are no spare registers. So we'd need
|
||||
// to check all store instruction to not alias with the stack.
|
||||
follow = true;
|
||||
destination = code[caller].address + 4;
|
||||
found_call = false;
|
||||
code[i].skip = true;
|
||||
code[i].branchTo = code[caller].address + 4;
|
||||
if ((inst.BO & BO_DONT_DECREMENT_FLAG) && (inst.BO & BO_DONT_CHECK_CONDITION) &&
|
||||
numFollows < BRANCH_FOLLOWING_THRESHOLD)
|
||||
{
|
||||
// bclrx with unconditional branch = return
|
||||
// Follow it if we can propagate the LR value of the last CALL instruction.
|
||||
// Through it would be easy to track the upper level of call/return,
|
||||
// we can't guarantee the LR value. The PPC ABI forces all functions to push
|
||||
// the LR value on the stack as there are no spare registers. So we'd need
|
||||
// to check all store instruction to not alias with the stack.
|
||||
follow = true;
|
||||
found_call = false;
|
||||
code[i].skip = true;
|
||||
|
||||
// Skip the RET, so also don't generate the stack entry for the BLR optimization.
|
||||
code[caller].skipLRStack = true;
|
||||
// Skip the RET, so also don't generate the stack entry for the BLR optimization.
|
||||
code[caller].skipLRStack = true;
|
||||
}
|
||||
}
|
||||
else if (inst.OPCD == 31 && inst.SUBOP10 == 467)
|
||||
{
|
||||
|
@ -792,11 +874,14 @@ u32 PPCAnalyzer::Analyze(u32 address, CodeBlock* block, CodeBuffer* buffer, std:
|
|||
}
|
||||
}
|
||||
|
||||
if (follow)
|
||||
code[i].branchIsIdleLoop =
|
||||
code[i].branchTo == block->m_address && IsBusyWaitLoop(block, code, i);
|
||||
|
||||
if (follow && numFollows < BRANCH_FOLLOWING_THRESHOLD)
|
||||
{
|
||||
// Follow the unconditional branch.
|
||||
numFollows++;
|
||||
address = destination;
|
||||
address = code[i].branchTo;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
@ -27,13 +27,14 @@ struct CodeOp // 16B
|
|||
UGeckoInstruction inst;
|
||||
GekkoOPInfo* opinfo;
|
||||
u32 address;
|
||||
u32 branchTo; // if 0, not a branch
|
||||
int branchToIndex; // index of target block
|
||||
u32 branchTo; // if UINT32_MAX, not a branch
|
||||
BitSet32 regsOut;
|
||||
BitSet32 regsIn;
|
||||
BitSet32 fregsIn;
|
||||
s8 fregOut;
|
||||
bool isBranchTarget;
|
||||
bool branchUsesCtr;
|
||||
bool branchIsIdleLoop;
|
||||
bool wantsCR0;
|
||||
bool wantsCR1;
|
||||
bool wantsFPRF;
|
||||
|
@ -213,6 +214,7 @@ private:
|
|||
void ReorderInstructionsCore(u32 instructions, CodeOp* code, bool reverse, ReorderType type);
|
||||
void ReorderInstructions(u32 instructions, CodeOp* code);
|
||||
void SetInstructionStats(CodeBlock* block, CodeOp* code, const GekkoOPInfo* opinfo, u32 index);
|
||||
bool IsBusyWaitLoop(CodeBlock* block, CodeOp* code, size_t instructions);
|
||||
|
||||
// Options
|
||||
u32 m_options = 0;
|
||||
|
|
Loading…
Reference in New Issue