LLE JIT: Added another 9 DSP Load/Store instructions to the JIT. Fixed a couple bugs in the 32bit and Linux builds.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6599 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
parent
aecc4f67a1
commit
2a54c445a0
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@ -61,10 +61,11 @@ public:
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void decrement_addr_reg(int reg);
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void increase_addr_reg(int reg);
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void decrease_addr_reg(int reg);
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void dmem_write();
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void dmem_write_imm(u16 addr);
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void imem_read();
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void dmem_read();
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void dmem_read_imm(u16 addr);
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void dmem_write();
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void dmem_write_imm(u16 addr);
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// Ext command helpers
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void pushExtValueFromReg(u16 dreg, u16 sreg);
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@ -132,6 +133,15 @@ public:
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void lr(const UDSPInstruction opc);
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void sr(const UDSPInstruction opc);
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void si(const UDSPInstruction opc);
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void lrr(const UDSPInstruction opc);
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void lrrd(const UDSPInstruction opc);
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void lrri(const UDSPInstruction opc);
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void srr(const UDSPInstruction opc);
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void srrd(const UDSPInstruction opc);
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void srri(const UDSPInstruction opc);
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void ilrr(const UDSPInstruction opc);
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void ilrrd(const UDSPInstruction opc);
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void ilrri(const UDSPInstruction opc);
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// Arithmetic
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void addr(const UDSPInstruction opc);
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@ -178,9 +178,9 @@ const DSPOPCTemplate opcodes[] =
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{"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true},
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{"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true},
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{"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, &DSPEmitter::ilrr, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, &DSPEmitter::ilrrd, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, &DSPEmitter::ilrri, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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{"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false},
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// LOOPS
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@ -190,14 +190,14 @@ const DSPOPCTemplate opcodes[] =
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{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true},
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// load and store value pointed by indexing reg and increment; LRR/SRR variants
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{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, &DSPEmitter::lrr, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, &DSPEmitter::lrrd, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, &DSPEmitter::lrri, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false},
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{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, &DSPEmitter::srr, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, &DSPEmitter::srrd, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, &DSPEmitter::srri, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false},
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//2
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@ -36,7 +36,7 @@ void DSPEmitter::srs(const UDSPInstruction opc)
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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MOV(32, R(EAX), M(&g_dsp.r[DSP_REG_CR]));
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MOVZX(32, 8, EAX, M(&g_dsp.r[DSP_REG_CR]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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@ -57,7 +57,7 @@ void DSPEmitter::lrs(const UDSPInstruction opc)
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u8 reg = ((opc >> 8) & 0x7) + 0x18;
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOV(32, R(ECX), M(&g_dsp.r[DSP_REG_CR]));
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MOVZX(32, 8, ECX, M(&g_dsp.r[DSP_REG_CR]));
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SHL(16, R(ECX), Imm8(8));
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OR(8, R(ECX), Imm8(opc & 0xFF));
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dmem_read();
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@ -118,47 +118,65 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// 0001 1000 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrr(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrr(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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}
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// LRRD $D, @$S
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// 0001 1000 1ssd dddd
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// Move value from data memory pointed by addressing register $S toregister $D.
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// Decrement register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrrd(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrrd(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_decrement_addr_reg(sreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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decrement_addr_reg(sreg);
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}
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// LRRI $D, @$S
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// 0001 1001 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Increment register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrri(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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void DSPEmitter::lrri(const UDSPInstruction opc)
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{
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u8 sreg = (opc >> 5) & 0x3;
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u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_increment_addr_reg(sreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, R(ECX));
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#else
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MOVZX(64, 16, ECX, R(ECX));
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#endif
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dmem_read();
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dsp_op_write_reg(dreg, EAX);
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dsp_conditional_extend_accum(dreg);
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increment_addr_reg(sreg);
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}
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// LRRN $D, @$S
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// 0001 1001 1ssd dddd
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@ -181,45 +199,62 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// Store value from source register $S to a memory location pointed by
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// addressing register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srr(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srr(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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}
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// SRRD @$D, $S
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// 0001 1010 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Decrement register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srrd(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srrd(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_decrement_addr_reg(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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decrement_addr_reg(dreg);
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}
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// SRRI @$D, $S
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// 0001 1011 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Increment register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srri(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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void DSPEmitter::srri(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x3;
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u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_increment_addr_reg(dreg);
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//}
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dsp_op_read_reg(sreg, ECX);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
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#endif
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dmem_write();
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increment_addr_reg(dreg);
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}
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// SRRN @$D, $S
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// 0001 1011 1dds ssss
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@ -240,42 +275,78 @@ void DSPEmitter::si(const UDSPInstruction opc)
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// 0000 001d 0001 00ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m.
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//void DSPEmitter::ilrr(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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void DSPEmitter::ilrr(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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//}
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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#endif
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imem_read();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[dreg]), R(EAX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,dreg*2), R(RAX));
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#endif
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dsp_conditional_extend_accum(dreg);
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}
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// ILRRD $acD.m, @$arS
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// 0000 001d 0001 01ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
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//void DSPEmitter::ilrrd(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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void DSPEmitter::ilrrd(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x3;
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u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_decrement_addr_reg(reg);
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//}
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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#endif
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imem_read();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[dreg]), R(EAX));
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||||
#else
|
||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
||||
#endif
|
||||
dsp_conditional_extend_accum(dreg);
|
||||
dsp_decrement_addr_reg(reg);
|
||||
}
|
||||
|
||||
// ILRRI $acD.m, @$S
|
||||
// 0000 001d 0001 10ss
|
||||
// Move value from instruction memory pointed by addressing register
|
||||
// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
|
||||
//void DSPEmitter::ilrri(const UDSPInstruction opc)
|
||||
//{
|
||||
// u16 reg = opc & 0x3;
|
||||
// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||
void DSPEmitter::ilrri(const UDSPInstruction opc)
|
||||
{
|
||||
u16 reg = opc & 0x3;
|
||||
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
|
||||
|
||||
// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
|
||||
// dsp_conditional_extend_accum(dreg);
|
||||
// g_dsp.r[reg] = dsp_increment_addr_reg(reg);
|
||||
//}
|
||||
#ifdef _M_IX86 // All32
|
||||
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
|
||||
#else
|
||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
|
||||
#endif
|
||||
imem_read();
|
||||
#ifdef _M_IX86 // All32
|
||||
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
|
||||
#else
|
||||
MOV(64, R(R11), ImmPtr(g_dsp.r));
|
||||
MOV(16, MDisp(R11,dreg*2), R(RAX));
|
||||
#endif
|
||||
dsp_conditional_extend_accum(dreg);
|
||||
dsp_increment_addr_reg(reg);
|
||||
}
|
||||
|
||||
// ILRRN $acD.m, @$arS
|
||||
// 0000 001d 0001 11ss
|
||||
|
|
|
|||
|
|
@ -338,7 +338,12 @@ void DSPEmitter::dmem_write_imm(u16 addr)
|
|||
switch (addr >> 12)
|
||||
{
|
||||
case 0x0: // 0xxx DRAM
|
||||
#ifdef _M_IX86 // All32
|
||||
MOV(16, M(&g_dsp.dram[addr & DSP_DRAM_MASK]), R(ECX));
|
||||
#else
|
||||
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
||||
MOV(16, MDisp(RDX,(addr & DSP_DRAM_MASK)*2), R(ECX));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0xf: // Fxxx HW regs
|
||||
|
|
@ -352,8 +357,40 @@ void DSPEmitter::dmem_write_imm(u16 addr)
|
|||
}
|
||||
}
|
||||
|
||||
// EAX - the result of the read (used by caller)
|
||||
// ECX - the address to read
|
||||
// In: ECX - the address to read
|
||||
// Out: EAX - the result of the read (used by caller)
|
||||
// ESI - Base
|
||||
void DSPEmitter::imem_read()
|
||||
{
|
||||
// if (addr == 0)
|
||||
CMP(16, R(ECX), Imm16(0x0fff));
|
||||
FixupBranch irom = J_CC(CC_A);
|
||||
// return g_dsp.iram[addr & DSP_IRAM_MASK];
|
||||
AND(16, R(ECX), Imm16(DSP_IRAM_MASK));
|
||||
#ifdef _M_X64
|
||||
MOV(64, R(ESI), ImmPtr(g_dsp.iram));
|
||||
#else
|
||||
MOV(32, R(ESI), ImmPtr(g_dsp.iram));
|
||||
#endif
|
||||
MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
|
||||
|
||||
FixupBranch end = J();
|
||||
SetJumpTarget(irom);
|
||||
// else if (addr == 0x8)
|
||||
// return g_dsp.irom[addr & DSP_IROM_MASK];
|
||||
AND(16, R(ECX), Imm16(DSP_IROM_MASK));
|
||||
#ifdef _M_X64
|
||||
MOV(64, R(ESI), ImmPtr(g_dsp.irom));
|
||||
#else
|
||||
MOV(32, R(ESI), ImmPtr(g_dsp.irom));
|
||||
#endif
|
||||
MOV(16, R(EAX), MComplex(ESI,ECX,2,0));
|
||||
|
||||
SetJumpTarget(end);
|
||||
}
|
||||
|
||||
// In: ECX - the address to read
|
||||
// Out: EAX - the result of the read (used by caller)
|
||||
// ESI - Base
|
||||
// Trashes R11 on gdsp_ifx_read
|
||||
void DSPEmitter::dmem_read()
|
||||
|
|
@ -399,11 +436,21 @@ void DSPEmitter::dmem_read_imm(u16 addr)
|
|||
switch (addr >> 12)
|
||||
{
|
||||
case 0x0: // 0xxx DRAM
|
||||
#ifdef _M_IX86 // All32
|
||||
MOV(16, R(EAX), M(&g_dsp.dram[addr & DSP_DRAM_MASK]));
|
||||
#else
|
||||
MOV(64, R(RDX), ImmPtr(g_dsp.dram));
|
||||
MOV(16, R(EAX), MDisp(RDX,(addr & DSP_DRAM_MASK)*2));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0x1: // 1xxx COEF
|
||||
#ifdef _M_IX86 // All32
|
||||
MOV(16, R(EAX), Imm16(g_dsp.coef[addr & DSP_COEF_MASK]));
|
||||
#else
|
||||
MOV(64, R(RDX), ImmPtr(g_dsp.coef));
|
||||
MOV(16, R(EAX), MDisp(RDX,(addr & DSP_COEF_MASK)*2));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0xf: // Fxxx HW regs
|
||||
|
|
|
|||
Loading…
Reference in New Issue