DSPLLE got rid of exception in progress hack.

I didn't get any change in behaviour though.


git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3621 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee 2009-06-30 10:10:30 +00:00
parent fc63424bce
commit 292b3f675f
4 changed files with 20 additions and 16 deletions

View File

@ -157,11 +157,10 @@ void DSPCore_CheckExternalInterrupt()
// check if there is an external interrupt // check if there is an external interrupt
if (g_dsp.cr & CR_EXTERNAL_INT) if (g_dsp.cr & CR_EXTERNAL_INT)
{ {
if (dsp_SR_is_flag_set(FLAG_ENABLE_INTERUPT) && (g_dsp.exception_in_progress_hack == false)) if (dsp_SR_is_flag_set(SR_INT_ENABLE))
{ {
// level 7 is the interrupt exception // level 7 is the interrupt exception. is it?
DSPCore_SetException(7); // DSPCore_SetException(7);
g_dsp.cr &= ~CR_EXTERNAL_INT; g_dsp.cr &= ~CR_EXTERNAL_INT;
} }
} }
@ -170,21 +169,20 @@ void DSPCore_CheckExternalInterrupt()
void DSPCore_CheckExceptions() void DSPCore_CheckExceptions()
{ {
// check exceptions // check exceptions
if ((g_dsp.exceptions != 0) && (!g_dsp.exception_in_progress_hack)) if (g_dsp.exceptions != 0)
{ {
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
if (g_dsp.exceptions & (1 << i)) if (g_dsp.exceptions & (1 << i) && dsp_SR_is_flag_set(SR_INT_ENABLE))
{ {
_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc); dsp_reg_store_stack(DSP_STACK_C, g_dsp.pc);
dsp_reg_store_stack(DSP_STACK_D, g_dsp.r[DSP_REG_SR]); dsp_reg_store_stack(DSP_STACK_D, g_dsp.r[DSP_REG_SR]);
g_dsp.r[DSP_REG_SR] &= ~ SR_INT_ENABLE;
g_dsp.pc = i * 2; g_dsp.pc = i * 2;
g_dsp.exceptions &= ~(1 << i); g_dsp.exceptions &= ~(1 << i);
g_dsp.exception_in_progress_hack = true;
break; break;
} }
} }

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@ -75,6 +75,15 @@ void gdsp_mbox_write_h(u8 mbx, u16 val)
gdsp_mbox[mbx][0] = val & 0x7fff; gdsp_mbox[mbx][0] = val & 0x7fff;
if (DSPHost_OnThread()) if (DSPHost_OnThread())
g_CriticalSection.Leave(); g_CriticalSection.Leave();
if (mbx == GDSP_MBOX_DSP)
{
DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
} else {
// mailbox
DSPCore_SetException(7);
}
} }
@ -91,7 +100,8 @@ void gdsp_mbox_write_l(u8 mbx, u16 val)
{ {
DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc); DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
} else { } else {
// Trigger exception? // mailbox
DSPCore_SetException(7);
} }
} }

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@ -21,7 +21,6 @@
#include "DSPTables.h" #include "DSPTables.h"
#define DSP_REG_MASK 0x1f #define DSP_REG_MASK 0x1f
#define FLAG_ENABLE_INTERUPT 11
namespace DSPInterpreter { namespace DSPInterpreter {

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@ -121,13 +121,10 @@ void ret(const UDSPInstruction& opc)
// Return from exception. Pops stored status register $sr from data stack // Return from exception. Pops stored status register $sr from data stack
// $st1 and program counter PC from call stack $st0 and sets $pc to this // $st1 and program counter PC from call stack $st0 and sets $pc to this
// location. // location.
// FIXME: is it also conditional? unknown opcodes 0x02fx
void rti(const UDSPInstruction& opc) void rti(const UDSPInstruction& opc)
{ {
g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D); g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C); g_dsp.pc = dsp_reg_load_stack(DSP_STACK_C);
g_dsp.exception_in_progress_hack = false;
} }
// HALT // HALT