Merge pull request #12278 from JosJuice/jitarm64-gpr-loop
JitArm64: Optimize Arm64GPRCache::FlushRegisters/FlushCRRegisters
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commit
2869a4c168
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@ -241,63 +241,57 @@ void Arm64GPRCache::FlushRegister(size_t index, bool maintain_state, ARM64Reg tm
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void Arm64GPRCache::FlushRegisters(BitSet32 regs, bool maintain_state, ARM64Reg tmp_reg)
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{
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for (size_t i = 0; i < GUEST_GPR_COUNT; ++i)
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for (int i : regs)
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{
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if (regs[i])
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{
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ASSERT_MSG(DYNA_REC, m_guest_registers[GUEST_GPR_OFFSET + i].GetType() != RegType::Discarded,
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"Attempted to flush discarded register");
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ASSERT_MSG(DYNA_REC, m_guest_registers[GUEST_GPR_OFFSET + i].GetType() != RegType::Discarded,
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"Attempted to flush discarded register");
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if (i + 1 < GUEST_GPR_COUNT && regs[i + 1])
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if (i + 1 < GUEST_GPR_COUNT && regs[i + 1])
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{
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// We've got two guest registers in a row to store
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OpArg& reg1 = m_guest_registers[GUEST_GPR_OFFSET + i];
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OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1];
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if (reg1.IsDirty() && reg2.IsDirty() && reg1.GetType() == RegType::Register &&
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reg2.GetType() == RegType::Register)
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{
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// We've got two guest registers in a row to store
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OpArg& reg1 = m_guest_registers[GUEST_GPR_OFFSET + i];
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OpArg& reg2 = m_guest_registers[GUEST_GPR_OFFSET + i + 1];
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if (reg1.IsDirty() && reg2.IsDirty() && reg1.GetType() == RegType::Register &&
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reg2.GetType() == RegType::Register)
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const size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
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if (ppc_offset <= 252)
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{
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const size_t ppc_offset = GetGuestByIndex(i).ppc_offset;
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if (ppc_offset <= 252)
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ARM64Reg RX1 = R(GetGuestByIndex(i));
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ARM64Reg RX2 = R(GetGuestByIndex(i + 1));
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m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset));
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if (!maintain_state)
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{
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ARM64Reg RX1 = R(GetGuestByIndex(i));
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ARM64Reg RX2 = R(GetGuestByIndex(i + 1));
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m_emit->STP(IndexType::Signed, RX1, RX2, PPC_REG, u32(ppc_offset));
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if (!maintain_state)
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{
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UnlockRegister(EncodeRegTo32(RX1));
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UnlockRegister(EncodeRegTo32(RX2));
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reg1.Flush();
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reg2.Flush();
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}
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++i;
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continue;
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UnlockRegister(EncodeRegTo32(RX1));
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UnlockRegister(EncodeRegTo32(RX2));
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reg1.Flush();
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reg2.Flush();
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}
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++i;
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continue;
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}
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}
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FlushRegister(GUEST_GPR_OFFSET + i, maintain_state, tmp_reg);
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}
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FlushRegister(GUEST_GPR_OFFSET + i, maintain_state, tmp_reg);
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}
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}
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void Arm64GPRCache::FlushCRRegisters(BitSet32 regs, bool maintain_state, ARM64Reg tmp_reg)
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void Arm64GPRCache::FlushCRRegisters(BitSet8 regs, bool maintain_state, ARM64Reg tmp_reg)
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{
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for (size_t i = 0; i < GUEST_CR_COUNT; ++i)
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for (int i : regs)
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{
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if (regs[i])
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{
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ASSERT_MSG(DYNA_REC, m_guest_registers[GUEST_CR_OFFSET + i].GetType() != RegType::Discarded,
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"Attempted to flush discarded register");
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ASSERT_MSG(DYNA_REC, m_guest_registers[GUEST_CR_OFFSET + i].GetType() != RegType::Discarded,
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"Attempted to flush discarded register");
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FlushRegister(GUEST_CR_OFFSET + i, maintain_state, tmp_reg);
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}
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FlushRegister(GUEST_CR_OFFSET + i, maintain_state, tmp_reg);
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}
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}
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void Arm64GPRCache::Flush(FlushMode mode, ARM64Reg tmp_reg)
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{
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FlushRegisters(BitSet32(~0U), mode == FlushMode::MaintainState, tmp_reg);
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FlushCRRegisters(BitSet32(~0U), mode == FlushMode::MaintainState, tmp_reg);
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FlushRegisters(BitSet32(0xFFFFFFFF), mode == FlushMode::MaintainState, tmp_reg);
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FlushCRRegisters(BitSet8(0xFF), mode == FlushMode::MaintainState, tmp_reg);
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}
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ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg)
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@ -330,7 +330,7 @@ public:
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FlushRegisters(regs, false, tmp_reg);
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}
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void StoreCRRegisters(BitSet32 regs, Arm64Gen::ARM64Reg tmp_reg = Arm64Gen::ARM64Reg::INVALID_REG)
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void StoreCRRegisters(BitSet8 regs, Arm64Gen::ARM64Reg tmp_reg = Arm64Gen::ARM64Reg::INVALID_REG)
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{
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FlushCRRegisters(regs, false, tmp_reg);
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}
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@ -365,7 +365,7 @@ private:
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void BindToRegister(const GuestRegInfo& guest_reg, bool will_read, bool will_write = true);
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void FlushRegisters(BitSet32 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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void FlushCRRegisters(BitSet32 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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void FlushCRRegisters(BitSet8 regs, bool maintain_state, Arm64Gen::ARM64Reg tmp_reg);
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};
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class Arm64FPRCache : public Arm64RegCache
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