Jit_LoadStorePaired: Make psq_st PIE-compliant
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@ -89,12 +89,12 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
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// 0b0011111100000111, or 0x3F07.
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MOV(32, R(RSCRATCH2), Imm32(0x3F07));
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AND(32, R(RSCRATCH2), PPCSTATE(spr[SPR_GQR0 + i]));
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MOVZX(32, 8, RSCRATCH, R(RSCRATCH2));
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if (w)
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CALLptr(MScaled(RSCRATCH, SCALE_8, PtrOffset(asm_routines.singleStoreQuantized)));
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else
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CALLptr(MScaled(RSCRATCH, SCALE_8, PtrOffset(asm_routines.pairedStoreQuantized)));
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LEA(64, RSCRATCH, M(w ? asm_routines.singleStoreQuantized : asm_routines.pairedStoreQuantized));
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// 8-bit operations do not zero upper 32-bits of 64-bit registers.
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// Here we know that RSCRATCH's least significant byte is zero.
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OR(8, R(RSCRATCH), R(RSCRATCH2));
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SHL(8, R(RSCRATCH), Imm8(3));
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CALLptr(MatR(RSCRATCH));
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}
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if (update && jo.memcheck)
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@ -243,7 +243,8 @@ constexpr std::array<u8, 8> sizes{{32, 0, 0, 0, 8, 16, 8, 16}};
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void CommonAsmRoutines::GenQuantizedStores()
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{
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pairedStoreQuantized = reinterpret_cast<const u8**>(const_cast<u8*>(AlignCode16()));
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// Aligned to 256 bytes as least significant byte needs to be zero (See: Jit64::psq_stXX).
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pairedStoreQuantized = reinterpret_cast<const u8**>(const_cast<u8*>(AlignCodeTo(256)));
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ReserveCodeSpace(8 * sizeof(u8*));
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for (int type = 0; type < 8; type++)
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@ -253,7 +254,8 @@ void CommonAsmRoutines::GenQuantizedStores()
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// See comment in header for in/outs.
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void CommonAsmRoutines::GenQuantizedSingleStores()
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{
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singleStoreQuantized = reinterpret_cast<const u8**>(const_cast<u8*>(AlignCode16()));
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// Aligned to 256 bytes as least significant byte needs to be zero (See: Jit64::psq_stXX).
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singleStoreQuantized = reinterpret_cast<const u8**>(const_cast<u8*>(AlignCodeTo(256)));
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ReserveCodeSpace(8 * sizeof(u8*));
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for (int type = 0; type < 8; type++)
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