some more UCode stuff

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@815 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
fires.gc 2008-10-09 20:20:25 +00:00
parent 7c4be7a975
commit 2521c52847
2 changed files with 59 additions and 46 deletions

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@ -7,18 +7,17 @@
// //
0x0000 0x0000 // RightBuffer
0x0140 0x0140 // LeftBuffer
0x0280 // outbuffer left and right... each channel is 0x140 samples long 0x0280
0x0400 0x0400 // Opcode_14() interleaves the buffer to this address
0x0540 0x0540
0x0680 0x0680
0x07C0 0x07C0
0x0900 0x0900
0x0A40 0x0A40
0x0B80 to 0x0C40 CurrentPB 0x0B80 to 0x0C40 // CurrentPB
0x0B87
// addresses to buffers // addresses to buffers
0x0E08 // initialized to 0x0000 0x0E08 // initialized to 0x0000
@ -914,6 +913,8 @@ Main()
// //
043b 8c00 CLR15 043b 8c00 CLR15
043c 8a00 M2 043c 8a00 M2
// send the 0x280 to 0x500 to CPU RAM
043d 8100 CLR $30 043d 8100 CLR $30
043e 8970 CLR.L $31 : $30, @$0 043e 8970 CLR.L $31 : $30, @$0
043f 191f LRRI $31, @$0 043f 191f LRRI $31, @$0
@ -929,8 +930,12 @@ Main()
044e 0082 0140 LRI $2, #0x0140 044e 0082 0140 LRI $2, #0x0140
0450 0099 0080 LRI $25, #0x0080 0450 0099 0080 LRI $25, #0x0080
0452 02bf 055c CALL 0x055c // Wait for DMA control reg 0452 02bf 055c CALL 0x055c // Wait for DMA control reg
// interleave loop and DMA the buffer to CPU... call innerloop 5 times (5 * 32Byte)
0454 1105 046c BLOOPI #0x05, 0x046c 0454 1105 046c BLOOPI #0x05, 0x046c
0456 1f61 MRR $27, $1 0456 1f61 MRR $27, $1
// interleave 32 shorts (from left and right buffer)
0457 1120 045e BLOOPI #0x20, 0x045e 0457 1120 045e BLOOPI #0x20, 0x045e
0459 8972 CLR.L $31 : $30, @$2 0459 8972 CLR.L $31 : $30, @$2
045a 195c LRRI $28, @$2 045a 195c LRRI $28, @$2
@ -938,6 +943,8 @@ Main()
045c 197d LRRI $29, @$3 045c 197d LRRI $29, @$3
045d f131 LSL16.S $31 : @$1, $30 045d f131 LSL16.S $31 : @$1, $30
045e 8139 CLR.S $30 : @$1, $31 045e 8139 CLR.S $30 : @$1, $31
// end: innerloop
045f 8900 CLR $31 045f 8900 CLR $31
0460 6800 MOVAX $30, $24 0460 6800 MOVAX $30, $24
0461 2ece SRS @DSMAH, $30 0461 2ece SRS @DSMAH, $30
@ -946,15 +953,18 @@ Main()
0464 2fcd SRS @DSPA, $31 0464 2fcd SRS @DSPA, $31
0465 0f01 LRIS $31, #0x01 0465 0f01 LRIS $31, #0x01
0466 2fc9 SRS @DSCR, $31 0466 2fc9 SRS @DSCR, $31
0467 1ff9 MRR $31, $25 0467 1ff9 MRR $31, $25 // $25 is const 0x80
0468 2fcb SRS @DSBL, $31 0468 2fcb SRS @DSBL, $31
0469 7200 ADDAXL $30, $25 0469 7200 ADDAXL $30, $25
046a 1f5e MRR $26, $30 046a 1f5e MRR $26, $30
046b 1f1c MRR $24, $28 046b 1f1c MRR $24, $28
046c 8100 CLR $30 046c 8100 CLR $30
// end: outerloop (strange because shouldnt we wait to the DMA transfer all the time??)
046d 26c9 LRS $30, @DSCR 046d 26c9 LRS $30, @DSCR
046e 02a0 0004 ANDCF $30, #0x0004 046e 02a0 0004 ANDCF $30, #0x0004
0470 029c 046d JZR 0x046d // wait for DMA loop 0470 029c 046d JZR 0x046d // wait for DMA loop
0472 029f 0068 JMP 0x0068 // Return to message loop. 0472 029f 0068 JMP 0x0068 // Return to message loop.
// Opcode_11() - not implemented // Opcode_11() - not implemented

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@ -181,6 +181,7 @@
// Large mixer function - called a lot by AX // Large mixer function - called a lot by AX
// Prolly simple Stereo Mixer
80e7 8150 CLR.L $AC0.M : $AX0.H, @$R00 80e7 8150 CLR.L $AC0.M : $AX0.H, @$R00
80e8 8949 CLR.L $AC1.M : $AX1.L, @$R01 80e8 8949 CLR.L $AC1.M : $AX1.L, @$R01
80e9 b072 MULX.L $AX0.H, $AX1.L : $AC0.M, @$R02 80e9 b072 MULX.L $AX0.H, $AX1.L : $AC0.M, @$R02
@ -316,6 +317,8 @@
816b 9909 ASR16.IR $AC1.M : $R01 816b 9909 ASR16.IR $AC1.M : $R01
816c 1b7f SRRI @$R03, $AC1.M 816c 1b7f SRRI @$R03, $AC1.M
816d 812b CLR.S $AC0.M : @$R03, $AC1.L 816d 812b CLR.S $AC0.M : @$R03, $AC1.L
816e 1c04 MRR $R00, $R04 816e 1c04 MRR $R00, $R04
816f 1c45 MRR $R02, $R05 816f 1c45 MRR $R02, $R05
8170 1c62 MRR $R03, $R02 8170 1c62 MRR $R03, $R02