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Merge pull request #9690 from Sintendo/jit64divwux 

Jit64: divwux - Prefer three-operand IMUL
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Mat M 2021-05-13 06:42:14 -04:00 committed by GitHub
parent 80ac36a712 2cafa0a960
commit 24b9a64c11
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 18 additions and 3 deletions
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21
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -1271,14 +1271,29 @@ void Jit64::divwux(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd);
if (d == a)
magic++;
// Use smallest magic number and shift amount possible
while ((magic & 1) == 0 && shift > 0)
{
MOV(32, R(RSCRATCH), Imm32(magic + 1));
magic >>= 1;
shift--;
}
// Three-operand IMUL sign extends the immediate to 64 bits, so we may only
// use it when the magic number has its most significant bit set to 0
if ((magic & 0x80000000) == 0)
{
IMUL(64, Rd, Ra, Imm32(magic));
}
else if (d == a)
{
MOV(32, R(RSCRATCH), Imm32(magic));
IMUL(64, Rd, R(RSCRATCH));
}
else
{
MOV(32, Rd, Imm32(magic + 1));
MOV(32, Rd, Imm32(magic));
IMUL(64, Rd, Ra);
}
SHR(64, Rd, Imm8(shift + 32));