Merge pull request #1703 from FioraAeterna/saveregs
JIT: free up a register by eliminating RCODE_POINTERS
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24a2ca4d28
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@ -39,7 +39,6 @@ void Jit64AsmRoutineManager::Generate()
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// Two statically allocated registers.
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MOV(64, R(RMEM), Imm64((u64)Memory::base));
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MOV(64, R(RCODE_POINTERS), Imm64((u64)jit->GetBlockCache()->GetCodePointers())); //It's below 2GB so 32 bits are good enough
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MOV(64, R(RPPCSTATE), Imm64((u64)&PowerPC::ppcState + 0x80));
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const u8* outerLoop = GetCodePtr();
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@ -85,6 +84,9 @@ void Jit64AsmRoutineManager::Generate()
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dispatcherNoCheck = GetCodePtr();
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MOV(32, R(RSCRATCH), PPCSTATE(pc));
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u64 icache = (u64)jit->GetBlockCache()->iCache.data();
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u64 icacheVmem = (u64)jit->GetBlockCache()->iCacheVMEM.data();
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u64 icacheEx = (u64)jit->GetBlockCache()->iCacheEx.data();
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u32 mask = 0;
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FixupBranch no_mem;
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FixupBranch exit_mem;
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@ -95,16 +97,31 @@ void Jit64AsmRoutineManager::Generate()
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TEST(32, R(RSCRATCH), Imm32(mask));
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no_mem = J_CC(CC_NZ);
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AND(32, R(RSCRATCH), Imm32(JIT_ICACHE_MASK));
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MOV(64, R(RSCRATCH2), Imm64((u64)jit->GetBlockCache()->iCache.data()));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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if (icache <= INT_MAX)
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{
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH, (s32)icache));
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}
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else
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{
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MOV(64, R(RSCRATCH2), Imm64(icache));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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}
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exit_mem = J();
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SetJumpTarget(no_mem);
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TEST(32, R(RSCRATCH), Imm32(JIT_ICACHE_VMEM_BIT));
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FixupBranch no_vmem = J_CC(CC_Z);
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AND(32, R(RSCRATCH), Imm32(JIT_ICACHE_MASK));
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MOV(64, R(RSCRATCH2), Imm64((u64)jit->GetBlockCache()->iCacheVMEM.data()));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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if (icacheVmem <= INT_MAX)
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{
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH, (s32)icacheVmem));
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}
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else
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{
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MOV(64, R(RSCRATCH2), Imm64(icacheVmem));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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}
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if (SConfig::GetInstance().m_LocalCoreStartupParameter.bWii) exit_vmem = J();
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SetJumpTarget(no_vmem);
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@ -113,8 +130,16 @@ void Jit64AsmRoutineManager::Generate()
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TEST(32, R(RSCRATCH), Imm32(JIT_ICACHE_EXRAM_BIT));
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FixupBranch no_exram = J_CC(CC_Z);
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AND(32, R(RSCRATCH), Imm32(JIT_ICACHEEX_MASK));
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MOV(64, R(RSCRATCH2), Imm64((u64)jit->GetBlockCache()->iCacheEx.data()));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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if (icacheEx <= INT_MAX)
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{
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH, (s32)icacheEx));
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}
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else
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{
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MOV(64, R(RSCRATCH2), Imm64(icacheEx));
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MOV(32, R(RSCRATCH), MComplex(RSCRATCH2, RSCRATCH, SCALE_1, 0));
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}
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SetJumpTarget(no_exram);
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}
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@ -124,8 +149,17 @@ void Jit64AsmRoutineManager::Generate()
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TEST(32, R(RSCRATCH), R(RSCRATCH));
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FixupBranch notfound = J_CC(CC_L);
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//grab from list and jump to it
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JMPptr(MComplex(RCODE_POINTERS, RSCRATCH, 8, 0));
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//grab from list and jump to it
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u64 codePointers = (u64)jit->GetBlockCache()->GetCodePointers();
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if (codePointers <= INT_MAX)
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{
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JMPptr(MScaled(RSCRATCH, 8, (s32)codePointers));
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}
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else
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{
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MOV(64, R(RSCRATCH2), Imm64(codePointers));
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JMPptr(MComplex(RSCRATCH2, RSCRATCH, 8, 0));
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}
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SetJumpTarget(notfound);
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//Ok, no block, let's jit
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@ -267,9 +267,9 @@ const int* GPRRegCache::GetAllocationOrder(size_t& count)
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{
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// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
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#ifdef _WIN32
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RSI, RDI, R13, R14, R8, R9, R10, R11, R12, RCX
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RSI, RDI, R13, R14, R15, R8, R9, R10, R11, R12, RCX
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#else
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R12, R13, R14, RSI, RDI, R8, R9, R10, R11, RCX
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R12, R13, R14, R15, RSI, RDI, R8, R9, R10, R11, RCX
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#endif
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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@ -39,8 +39,6 @@
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#define RSCRATCH_EXTRA RCX
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// RMEM points to the start of emulated memory.
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#define RMEM RBX
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// RCODE_POINTERS does what it says.
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#define RCODE_POINTERS R15
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// RPPCSTATE points to ppcState + 0x80. It's offset because we want to be able
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// to address as much as possible in a one-byte offset form.
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#define RPPCSTATE RBP
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