MMU: optimize PTE lookup code
Pull out calculation of PTE1 instead of comparing the separate parts.
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16e756cb39
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@ -713,52 +713,44 @@ static __forceinline u32 TranslatePageAddress(const u32 _Address, const XCheckTL
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// hash function no 1 "xor" .360
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u32 hash = (VSID ^ page_index);
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u32 pte1 = bswap((VSID << 7) | api | PTE1_V);
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for (int hash_func = 0; hash_func < 2; hash_func++)
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{
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// hash function no 2 "not" .360
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if (hash_func == 1)
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{
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// hash function no 2 "not" .360
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hash = ~hash;
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pte1 |= PTE1_H << 24;
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}
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u32 pteg_addr = ((hash & PowerPC::ppcState.pagetable_hashmask) << 6) | PowerPC::ppcState.pagetable_base;
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for (int i = 0; i < 8; i++)
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for (int i = 0; i < 8; i++, pteg_addr += 8)
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{
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u32 pte = bswap(*(u32*)&base_mem[pteg_addr]);
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bool pteh = (pte & PTE1_H) == 0;
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if (hash_func == 1)
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pteh = !pteh;
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if ((pte & PTE1_V) && pteh)
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if (pte1 == *(u32*)&base_mem[pteg_addr])
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{
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if (VSID == PTE1_VSID(pte) && (api == PTE1_API(pte)))
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UPTE2 PTE2;
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PTE2.Hex = bswap((*(u32*)&base_mem[(pteg_addr + 4)]));
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// set the access bits
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switch (_Flag)
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{
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UPTE2 PTE2;
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PTE2.Hex = bswap((*(u32*)&base_mem[(pteg_addr + 4)]));
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// set the access bits
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switch (_Flag)
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{
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case FLAG_NO_EXCEPTION: break;
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case FLAG_READ: PTE2.R = 1; break;
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case FLAG_WRITE: PTE2.R = 1; PTE2.C = 1; break;
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case FLAG_OPCODE: PTE2.R = 1; break;
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}
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if (_Flag != FLAG_NO_EXCEPTION)
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*(u32*)&base_mem[(pteg_addr + 4)] = bswap(PTE2.Hex);
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// We already updated the TLB entry if this was caused by a C bit.
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if (res != TLB_UPDATE_C)
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UpdateTLBEntry(_Flag, PTE2, _Address);
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return (PTE2.RPN << 12) | offset;
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case FLAG_NO_EXCEPTION: break;
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case FLAG_READ: PTE2.R = 1; break;
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case FLAG_WRITE: PTE2.R = 1; PTE2.C = 1; break;
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case FLAG_OPCODE: PTE2.R = 1; break;
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}
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if (_Flag != FLAG_NO_EXCEPTION)
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*(u32*)&base_mem[(pteg_addr + 4)] = bswap(PTE2.Hex);
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// We already updated the TLB entry if this was caused by a C bit.
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if (res != TLB_UPDATE_C)
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UpdateTLBEntry(_Flag, PTE2, _Address);
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return (PTE2.RPN << 12) | offset;
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}
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pteg_addr += 8;
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}
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}
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return 0;
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