JIT: optimize crclr special case of crxor
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@ -137,6 +137,7 @@ public:
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void GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate = false);
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// Clobbers RDX.
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void SetCRFieldBit(int field, int bit, Gen::X64Reg in);
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void ClearCRFieldBit(int field, int bit);
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// Generates a branch that will check if a given bit of a CR register part
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// is set or not.
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@ -89,6 +89,42 @@ void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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MOV(64, PPCSTATE(cr_val[field]), R(RSCRATCH2));
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}
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void Jit64::ClearCRFieldBit(int field, int bit)
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{
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MOV(64, R(RSCRATCH2), PPCSTATE(cr_val[field]));
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if (bit != CR_GT_BIT)
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{
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TEST(64, R(RSCRATCH2), R(RSCRATCH2));
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FixupBranch dont_clear_gt = J_CC(CC_NZ);
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BTS(64, R(RSCRATCH2), Imm8(63));
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SetJumpTarget(dont_clear_gt);
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}
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switch (bit)
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{
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case CR_SO_BIT: // set bit 61 to input
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BTR(64, R(RSCRATCH2), Imm8(61));
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break;
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case CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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SHR(64, R(RSCRATCH2), Imm8(32));
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SHL(64, R(RSCRATCH2), Imm8(32));
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break;
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case CR_GT_BIT: // set bit 63 to !input
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BTR(64, R(RSCRATCH2), Imm8(63));
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break;
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case CR_LT_BIT: // set bit 62 to input
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BTR(64, R(RSCRATCH2), Imm8(62));
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break;
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}
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BTS(64, R(RSCRATCH2), Imm8(32));
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MOV(64, PPCSTATE(cr_val[field]), R(RSCRATCH2));
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}
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FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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{
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switch (bit)
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@ -476,6 +512,13 @@ void Jit64::crXXX(UGeckoInstruction inst)
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JITDISABLE(bJITSystemRegistersOff);
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_dbg_assert_msg_(DYNA_REC, inst.OPCD == 19, "Invalid crXXX");
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// Special case: crclr
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if (inst.CRBA == inst.CRBB && inst.CRBA == inst.CRBD && inst.SUBOP10 == 193)
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{
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ClearCRFieldBit(inst.CRBD >> 2, 3 - (inst.CRBD & 3));
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return;
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}
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// TODO(delroth): Potential optimizations could be applied here. For
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// instance, if the two CR bits being loaded are the same, two loads are
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// not required.
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