From 5ea1cc5406fc5b3e287cc24c7eb5c2d9c3d19720 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 19 Aug 2023 20:57:32 +0200 Subject: [PATCH 1/2] JitArm64: Fix mcrxr Likely an incorrect translation of Jit64's LEA with SCALE_2. --- Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp index 3df2fea5fa..281568a55b 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp @@ -143,7 +143,7 @@ void JitArm64::mcrxr(UGeckoInstruction inst) LDRB(IndexType::Unsigned, WB, PPC_REG, PPCSTATE_OFF(xer_so_ov)); // [0 SO OV CA] - ADD(WA, WA, WB, ArithOption(WB, ShiftType::LSL, 2)); + ADD(WA, WA, WB, ArithOption(WB, ShiftType::LSL, 1)); // [SO OV CA 0] << 3 LSL(WA, WA, 4); From c70dcf99dd7b434d5196feb47f2a6e87bb34234b Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 19 Aug 2023 21:13:56 +0200 Subject: [PATCH 2/2] Jit: Some mcrxr optimizations --- Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp | 4 ++-- .../Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp index 5992fe9f28..9a4d124ee8 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp @@ -588,8 +588,8 @@ void Jit64::mcrxr(UGeckoInstruction inst) MOV(64, CROffset(inst.CRFD), R(RSCRATCH)); // Clear XER[0-3] - MOV(8, PPCSTATE(xer_ca), Imm8(0)); - MOV(8, PPCSTATE(xer_so_ov), Imm8(0)); + static_assert(PPCSTATE_OFF(xer_ca) + 1 == PPCSTATE_OFF(xer_so_ov)); + MOV(16, PPCSTATE(xer_ca), Imm8(0)); } void Jit64::crXXX(UGeckoInstruction inst) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp index 281568a55b..690b6be62c 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp @@ -143,7 +143,7 @@ void JitArm64::mcrxr(UGeckoInstruction inst) LDRB(IndexType::Unsigned, WB, PPC_REG, PPCSTATE_OFF(xer_so_ov)); // [0 SO OV CA] - ADD(WA, WA, WB, ArithOption(WB, ShiftType::LSL, 1)); + BFI(WA, WB, 1, 2); // [SO OV CA 0] << 3 LSL(WA, WA, 4); @@ -151,8 +151,8 @@ void JitArm64::mcrxr(UGeckoInstruction inst) LDR(XB, XB, XA); // Clear XER[0-3] - STRB(IndexType::Unsigned, ARM64Reg::WZR, PPC_REG, PPCSTATE_OFF(xer_ca)); - STRB(IndexType::Unsigned, ARM64Reg::WZR, PPC_REG, PPCSTATE_OFF(xer_so_ov)); + static_assert(PPCSTATE_OFF(xer_ca) + 1 == PPCSTATE_OFF(xer_so_ov)); + STRH(IndexType::Unsigned, ARM64Reg::WZR, PPC_REG, PPCSTATE_OFF(xer_ca)); gpr.Unlock(WA); }