From 5ed3a5de22386848827ba11adfb706eca751a16b Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 31 May 2015 22:03:36 -0500 Subject: [PATCH] [AArch64] Minor bugfix and optimization. Fixes a bug in lfs where I was doing a rev64.16b when I needed to do a rev32.8b. Change a ld1r.4s to a ld1r.2s. Fix an issue where a fcvtl2 needed to be a fcvtl. Re-enabled psq_l, issue with flickering can't be reproduced anymore, so whatever. --- Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp | 6 +++--- .../Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp index c1ca1edc4a..fdce4dea7b 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp @@ -162,9 +162,9 @@ u32 JitArm64::EmitBackpatchRoutine(ARM64XEmitter* emit, u32 flags, bool fastmem, trouble_offset = (emit->GetCodePtr() - code_base) / 4; if (flags & BackPatchInfo::FLAG_SIZE_F32) { - float_emit.LD1R(32, RS, addr); - float_emit.REV64(8, RS, RS); - float_emit.FCVTL(64, RS, RS); + float_emit.LD1R(32, EncodeRegToDouble(RS), addr); + float_emit.REV32(8, EncodeRegToDouble(RS), EncodeRegToDouble(RS)); + float_emit.FCVTL(64, EncodeRegToDouble(RS), EncodeRegToDouble(RS)); } else { diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp index cba780332f..872e37d71e 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp @@ -21,7 +21,6 @@ void JitArm64::psq_l(UGeckoInstruction inst) INSTRUCTION_START JITDISABLE(bJITLoadStorePairedOff); FALLBACK_IF(jo.memcheck || !jo.fastmem); - FALLBACK_IF(true); // X30 is LR // X0 contains the scale