[AArch64] Implement twi and tw.
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078147d424
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1cb07ffc14
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@ -92,6 +92,7 @@ public:
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void mtsr(UGeckoInstruction inst);
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void mfsrin(UGeckoInstruction inst);
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void mtsrin(UGeckoInstruction inst);
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void twx(UGeckoInstruction inst);
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// LoadStore
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void icbi(UGeckoInstruction inst);
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@ -129,3 +129,65 @@ void JitArm64::mtsrin(UGeckoInstruction inst)
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gpr.Unlock(index);
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}
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void JitArm64::twx(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITIntegerOff);
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gpr.Flush(FlushMode::FLUSH_ALL);
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fpr.Flush(FlushMode::FLUSH_ALL);
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s32 a = inst.RA;
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ARM64Reg WA = gpr.GetReg();
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if (inst.OPCD == 3) // twi
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{
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if (inst.SIMM_16 >= 0 && inst.SIMM_16 < 4096)
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{
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// Can fit in immediate in to the instruction encoding
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CMP(gpr.R(a), inst.SIMM_16);
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}
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else
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{
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MOVI2R(WA, (s32)(s16)inst.SIMM_16);
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CMP(gpr.R(a), WA);
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}
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}
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else // tw
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{
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CMP(gpr.R(a), gpr.R(inst.RB));
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}
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std::vector<FixupBranch> fixups;
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CCFlags conditions[] = { CC_LT, CC_GT, CC_EQ, CC_VC, CC_VS };
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for (int i = 0; i < 5; i++)
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{
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if (inst.TO & (1 << i))
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{
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FixupBranch f = B(conditions[i]);
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fixups.push_back(f);
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}
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}
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FixupBranch dont_trap = B();
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for (const FixupBranch& fixup : fixups)
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{
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SetJumpTarget(fixup);
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}
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LDR(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, 24, 0); // Same as WA | EXCEPTION_PROGRAM
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STR(INDEX_UNSIGNED, WA, X29, PPCSTATE_OFF(Exceptions));
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MOVI2R(WA, js.compilerPC);
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// WA is unlocked in this function
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WriteExceptionExit(WA);
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SetJumpTarget(dont_trap);
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WriteExit(js.compilerPC + 4);
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}
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@ -42,7 +42,7 @@ static GekkoOPTemplate primarytable[] =
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{1, &JitArm64::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}},
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{2, &JitArm64::FallBackToInterpreter}, //"DynaBlock", OPTYPE_SYSTEM, 0}},
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{3, &JitArm64::Break}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}},
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{3, &JitArm64::twx}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}},
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{17, &JitArm64::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
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{7, &JitArm64::FallBackToInterpreter}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}},
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@ -279,7 +279,7 @@ static GekkoOPTemplate table31[] =
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{595, &JitArm64::mfsr}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}},
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{659, &JitArm64::mfsrin}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}},
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{4, &JitArm64::Break}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
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{4, &JitArm64::twx}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
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{598, &JitArm64::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}},
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{982, &JitArm64::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}},
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