diff --git a/Source/Core/DSPCore/Src/DSPCore.cpp b/Source/Core/DSPCore/Src/DSPCore.cpp
index 713c3f9111..1758c70bde 100644
--- a/Source/Core/DSPCore/Src/DSPCore.cpp
+++ b/Source/Core/DSPCore/Src/DSPCore.cpp
@@ -114,6 +114,9 @@ bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
 	g_dsp.r[DSP_REG_WR2] = 0xffff;
 	g_dsp.r[DSP_REG_WR3] = 0xffff;
 
+	g_dsp.r[DSP_REG_SR] |= SR_INT_ENABLE;
+	g_dsp.r[DSP_REG_SR] |= SR_EXT_INT_ENABLE;
+
 	g_dsp.cr = 0x804;
 	gdsp_ifx_init();
 
@@ -121,8 +124,8 @@ bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
 	// in new ucodes.
 	WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
 	DSPAnalyzer::Analyze();
-
 	step_event.Init();
+	
 	return true;
 }
 
@@ -188,9 +191,9 @@ void DSPCore_CheckExceptions()
 #endif
 		// check exceptions should it be 0..7 or 7..0?
 		for (int i = 0; i < 8; i++) {
-			// Seems exp int is not masked by sr_int_enable
+			// Seems exp int or reset are not masked by sr_int_enable 
 			if (g_dsp.exceptions & (1 << i)) {
-				if (dsp_SR_is_flag_set(SR_INT_ENABLE) || i == EXP_INT) {
+				if (dsp_SR_is_flag_set(SR_INT_ENABLE) || i == EXP_INT || i == EXP_RESET) {
 					_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
 					
 					// store pc and sr until RTI
diff --git a/Source/Core/DSPCore/Src/DSPHWInterface.cpp b/Source/Core/DSPCore/Src/DSPHWInterface.cpp
index 727fb8d54a..bd7f2b0cbd 100644
--- a/Source/Core/DSPCore/Src/DSPHWInterface.cpp
+++ b/Source/Core/DSPCore/Src/DSPHWInterface.cpp
@@ -247,6 +247,9 @@ void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
 	INFO_LOG(DSPLLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)\n", addr, dsp_addr, g_dsp.iram_crc);
 	g_dsp.iram_crc = DSPHost_CodeLoaded(g_dsp.cpu_ram + (addr & 0x0fffffff), size);
 	DSPAnalyzer::Analyze();
+	// This calls the reset functions, but it get some games stuck
+	// uncomment it to help with debugging
+	//	DSPCore_SetException(EXP_RESET);
 }