Add immediate tests for WriteNormalOp
also fix a bug in Bochs that was preventing adc from passing.
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@ -36,7 +36,7 @@ Ia_adcl_Ed_sIb = { "adc", "adcl", Ed, sIbd, XX, XX, 0 },
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Ia_adcl_Gd_Ed = { "adc", "adcl", Gd, Ed, XX, XX, 0 },
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Ia_adcq_Eq_Gq = { "adc", "adcq", Eq, Gq, XX, XX, 0 },
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Ia_adcq_Eq_sIb = { "adc", "adcq", Eq, sIbq, XX, XX, 0 },
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Ia_adcq_Eq_sId = { "adc", "adcq", Eq, Iq, XX, XX, 0 },
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Ia_adcq_Eq_sId = { "adc", "adcq", Eq, sIdq, XX, XX, 0 },
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Ia_adcq_Gq_Eq = { "adc", "adcq", Gq, Eq, XX, XX, 0 },
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Ia_adcq_RAX_sId = { "adc", "adcq", RAX_Reg, sIdq, XX, XX, 0 },
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Ia_adcw_AX_Iw = { "adc", "adcw", AX_Reg, Iw, XX, XX, 0 },
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@ -527,12 +527,14 @@ ONE_OP_ARITH_TEST(NEG)
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std::vector<NamedReg> regs; \
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std::string size; \
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std::string rax_name; \
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Gen::OpArg imm; \
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std::string immname; \
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} regsets[] = { \
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{ 8, reg8names, "byte", "al" }, \
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{ 8, reg8hnames, "byte", "al" }, \
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{ 16, reg16names, "word", "ax" }, \
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{ 32, reg32names, "dword", "eax" }, \
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{ 64, reg64names, "qword", "rax" }, \
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{ 8, reg8names, "byte", "al", Imm8(0xEF), "0xef" }, \
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{ 8, reg8hnames, "byte", "al", Imm8(0xEF), "0xef" }, \
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{ 16, reg16names, "word", "ax", Imm16(0xBEEF), "0xbeef" }, \
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{ 32, reg32names, "dword", "eax", Imm32(0xDEADBEEF), "0xdeadbeef" }, \
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{ 64, reg64names, "qword", "rax", Imm32(0xDEADBEEF), "0xffffffffdeadbeef" }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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@ -541,10 +543,12 @@ ONE_OP_ARITH_TEST(NEG)
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emitter->Name(regset.bits, R(RAX), R(r.reg)); \
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emitter->Name(regset.bits, R(r.reg), MatR(RAX)); \
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emitter->Name(regset.bits, MatR(RAX), R(r.reg)); \
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emitter->Name(regset.bits, R(r.reg), regset.imm); \
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ExpectDisassembly(#Name " " + r.name + ", " + regset.rax_name + " " \
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#Name " " + regset.rax_name + ", " + r.name + " " \
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#Name " " + r.name + ", " + regset.size + " ptr ds:[rax] " \
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#Name " " + regset.size + " ptr ds:[rax], " + r.name); \
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#Name " " + regset.size + " ptr ds:[rax], " + r.name + " " \
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#Name " " + r.name + ", " + regset.immname ); \
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} \
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}
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